公开(公告)号：US20230402453A1

公开(公告)日：2023-12-14

申请号：US18231510

申请日：2023-08-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  John J. ELLIS-MONAGHAN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC: H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L27/082 ,  H01L27/0647 ,  H01L29/737 ,  H01L29/0646

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US11841103B2

公开(公告)日：2023-12-12

申请号：US17226087

申请日：2021-04-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas Shellenberger ,  Michael Scalise

IPC: F16L41/08 ,  F16L41/02

CPC classification number: F16L41/08 ,  F16L41/02

Abstract: A pipe assembly is provided, the pipe assembly comprising a first pipe having a side opening on a side surface of the first pipe. A plate in the first pipe is arranged adjacent to the side opening and at an angle relative to a radial axis of the first pipe such that a first side of the plate may be lower than a second side. A vent hole may be proximal the side opening on the side surface of the first pipe.

公开(公告)号：US11837605B2

公开(公告)日：2023-12-05

申请号：US17644858

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tom Herrmann ,  Zhixing Zhao ,  Alban Zaka ,  Yiching Chen

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/7838

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

公开(公告)号：US11837547B2

公开(公告)日：2023-12-05

申请号：US17450324

申请日：2021-10-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Roderick Alan Augur ,  Yusheng Bian ,  Robert John Fox, III

IPC: H01L23/532 ,  H01L23/552 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L23/5226 ,  H01L23/552

Abstract: A photonic integrated circuit (PIC) die includes a silicon nitride optical component over an active region. Multiple interconnect layers are over the silicon nitride optical component, each of the multiple interconnect layers including a metal interconnect therein. At least one optical deflector is over the multiple interconnect layers and over the silicon nitride optical component. The optical deflector(s) may also include a contact passing therethrough to the interconnect layers, but do not include any other electrical interconnects. Each optical deflector may deflect light within an ambient light range of less than 570 nanometers (nm) to protect the silicon nitride optical component from light-induced degradation.

公开(公告)号：US20230384518A1

公开(公告)日：2023-11-30

申请号：US17828139

申请日：2022-05-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/30

CPC classification number: G02B6/1228 ,  G02B6/12004 ,  G02B6/305 ,  G02B2006/12147 ,  G02B2006/12121 ,  G02B2006/12111 ,  G02B2006/12097

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. The structure comprises an edge coupler including a first waveguide core and a second waveguide core adjacent to the first waveguide core in a lateral direction. The first waveguide core includes a first section with a first thickness and a first plurality of segments projecting in a vertical direction from the first section. The second waveguide core includes a second section with a second thickness and a second plurality of segments projecting in the vertical direction from the second section.

公开(公告)号：US20230369314A1

公开(公告)日：2023-11-16

申请号：US17662921

申请日：2022-05-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Rajendran Krishnasamy ,  Anupam Dutta ,  Anindya Nath ,  Xiangxiang Lu ,  Satyasuresh Vvss Choppalli ,  Lin Lin

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/0266

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

公开(公告)号：US20230367067A1

公开(公告)日：2023-11-16

申请号：US17741684

申请日：2022-05-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Rod Augur

IPC: G02B6/124 ,  G02B6/13 ,  G02B6/122

CPC classification number: G02B6/124 ,  G02B6/1228 ,  G02B6/13 ,  G02B2006/12107

Abstract: Structures for an edge coupler and methods of fabricating such structures. The structure comprises a substrate and a back-end-of-line edge coupler including a waveguide core and a grating positioned in a vertical direction between the substrate and the waveguide core. The first waveguide core includes a first longitudinal axis, the grating includes a second longitudinal axis and a plurality of segments positioned with a spaced-apart arrangement along the second longitudinal axis, and the second longitudinal axis is aligned substantially parallel to the first longitudinal axis.

公开(公告)号：US20230361127A1

公开(公告)日：2023-11-09

申请号：US18139981

申请日：2023-04-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert ,  Handoko Linewih

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

公开(公告)号：US11808996B1

公开(公告)日：2023-11-07

申请号：US17729244

申请日：2022-04-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/42

CPC classification number: G02B6/4206 ,  G02B6/42

Abstract: Photonics structures for a waveguide or an edge coupler and methods of fabricating a photonics structure for a waveguide or an edge coupler. The photonics structure includes a waveguide core having a first section, a second section longitudinally adjacent to the first section, first segments projecting in a vertical direction from the first section, and second segments projecting in the vertical direction from the second section. The first section of the waveguide core has a first thickness, and the second section of the waveguide core has a second thickness that is greater than the first thickness.

公开(公告)号：US11804542B2

公开(公告)日：2023-10-31

申请号：US17557176

申请日：2021-12-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Arkadiusz Malinowski ,  Jagar Singh ,  Mankyu Yang ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/165 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture. The structure includes: a substate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; and an extrinsic base region contacting the intrinsic base region.