公开(公告)号：US09224843B2

公开(公告)日：2015-12-29

申请号：US14673958

申请日：2015-03-31

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Qizhi Liu

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/306 ,  H01L21/465 ,  H01L21/762 ,  H01L29/165 ,  H01L29/732

CPC classification number: H01L29/7371 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/465 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.

公开(公告)号：US09111986B2

公开(公告)日：2015-08-18

申请号：US14151225

申请日：2014-01-09

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Peng Cheng ,  Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L21/338 ,  H01L29/73 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7371

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 在半导体衬底上形成本征基极层，在本征基极层上形成蚀刻停止层，在蚀刻停止层上形成非本征基极层。 形成沟槽，其穿过外部基极层到蚀刻停止层。 通过蚀刻对蚀刻停止层选择性的非本征基层形成沟槽。 通过蚀刻对本征基极层有选择性的蚀刻停止层，第一沟槽通过蚀刻停止层延伸到本征基极层。 在沟槽延伸通过蚀刻停止层之后，使用沟槽形成发射极。

公开(公告)号：US20150206961A1

公开(公告)日：2015-07-23

申请号：US14160630

申请日：2014-01-22

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James S. Dunn ,  Blaine J. Gross ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L21/28 ,  H01L29/165 ,  H01L29/15 ,  H01L29/06 ,  H01L21/02 ,  G06F17/50 ,  H01L29/161

CPC classification number: H01L29/808 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  H01L21/28026 ,  H01L21/306 ,  H01L21/8232 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66901 ,  H01L29/66924 ,  H01L29/7782 ,  H01L29/8124

Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

Abstract translation: 在包括衬底，沟道和上栅极层的层堆叠中形成的至少一个隔离沟槽限定沟道层中的沟道。 来自隔离沟槽的横向蚀刻可以在衬底和上部栅极层中形成侧向空腔，以基本上同时形成自对准的下部栅极和上部栅极。 下栅极切口通道，上栅极比通道窄，并且可以在通道的相对端形成源极和漏极。 因此，可以减小源极 - 漏极电容和栅极 - 漏极电容，从而提高所产生的FET的速度。

公开(公告)号：US20150137186A1

公开(公告)日：2015-05-21

申请号：US14083774

申请日：2013-11-19

Applicant: International Business Machines Corporation

Inventor： Robert K. Leidy ,  Mark D. Levy ,  Qizhi Liu ,  Gary L. Milo

IPC: H01L29/737 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance Ccb and collector resistance Rc are minimized within the resulting bipolar semiconductor device.

Abstract translation: 公开了一种沟槽形成技术，其中具有具有平面轮廓的第一侧壁和具有锯齿轮廓的第二侧壁的开口被蚀刻通过半导体层并进入半导体衬底。 然后，晶体湿法蚀刻工艺使半导体衬底内的开口的部分膨胀以形成沟槽。 由于侧壁的轮廓不同，因此不同的晶体取向，一个侧壁比另一个侧壁更快地蚀刻，导致不对称的沟槽。 还公开了一种双极半导体器件形成方法，其在形成沟槽绝缘区域时结合上述沟槽形成技术，该沟槽隔离区域切割外部基极区域并且围绕收集器基座。 沟槽的不对称性确保沟槽隔离区域具有相对较窄的宽度，从而确保集电极到基极电容Ccb和集电极电阻Rc在所得双极半导体器件内最小化。

公开(公告)号：US09029229B2

公开(公告)日：2015-05-12

申请号：US13904304

申请日：2013-05-29

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  Peng Cheng ,  Vibhor Jain ,  Vikas Kumar Kaushal ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L29/66242 ,  H01L29/7371

Abstract: Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g., a bipolar device) is formed incorporating the resulting monocrystalline second and third semiconductor layers.

Abstract translation: 公开了形成器件的器件和方法，其中第一开口的一对通过电介质层形成，第一半导体层形成到衬底中，并且在衬底内，每对的第一开口横向膨胀并且形成 相应的沟槽。 沉积电介质材料，填充第一开口的上部并产生沟槽隔离区。 沉积第二半导体层，并且通过第二半导体和电介质层形成第二开口，使第一半导体层的单晶部分暴露在每对第一开口之间。 第三半导体层在第二半导体层上的多晶部分和第一半导体层的暴露的单晶部分上的单晶部分外延沉积。 进行结晶退火，并且形成结合所得单晶第二和第三半导体层的器件（例如，双极器件）。

公开(公告)号：US09018754B2

公开(公告)日：2015-04-28

申请号：US14041716

申请日：2013-09-30

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Qizhi Liu ,  Zhenzhen Ye ,  Yan Zhang

IPC: H01L23/10 ,  H01L21/00 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/7624 ,  H01L21/76283

Abstract: An isolation structure can include a structure material with thermal conductivity greater than silicon dioxide, yet electrical conductivity such that the structure material can replace silicon dioxide as an insulator. At least one column can extend to a target layer from a top surface of a semiconductor device near an active area of the device. At least one lateral portion can extend from the column(s) substantially parallel to the target layer and can extend between multiple columns in the target layer, such as in a cavity formed by lateral etching. The structure material can include, for example, aluminum nitride (AlN).

Abstract translation: 隔离结构可以包括导热率大于二氧化硅的结构材料，但是导电性使得结构材料可以代替二氧化硅作为绝缘体。 至少一列可以从设备的有效区域附近的半导体器件的顶表面延伸到目标层。 至少一个横向部分可以从基本上平行于目标层的柱延伸并且可以在目标层中的多个柱之间延伸，例如在通过横向蚀刻形成的空腔中。 结构材料可以包括例如氮化铝（AlN）。

公开(公告)号：US20150108549A1

公开(公告)日：2015-04-23

申请号：US14059780

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/465 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.

公开(公告)号：US20150048478A1

公开(公告)日：2015-02-19

申请号：US14496430

申请日：2014-09-25

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/732 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 第一隔离结构形成在衬底中以限定器件区域的边界。 在器件区域中形成集电极，在器件区域形成第二隔离结构。 第二个隔离结构定义了收集器的边界。 第二隔离结构相对于第一隔离结构横向定位，以限定第一和第二隔离结构之间的器件区域的一部分。

公开(公告)号：US08956945B2

公开(公告)日：2015-02-17

申请号：US13757961

申请日：2013-02-04

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu

IPC: H01L21/331 ,  G06F17/50 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L29/732 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Abstract translation: 双极结型晶体管的器件结构，制造方法和设计结构。 在衬底中形成第一隔离结构以限定器件区域的边界。 在器件区域中形成集电极，在器件区域形成第二隔离结构。 第二个隔离结构定义了收集器的边界。 第二隔离结构相对于第一隔离结构横向定位，以限定第一和第二隔离结构之间的器件区域的一部分。

公开(公告)号：US20150008558A1

公开(公告)日：2015-01-08

申请号：US14495057

申请日：2014-09-24

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Qizhi Liu

IPC: H01L29/735 ,  H01L29/06 ,  H01L29/10 ,  G06F17/50

CPC classification number: H01L29/735 ,  G06F17/5045 ,  H01L27/0823 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732

Abstract: Device structures and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 在基板上形成本征基底，在本征基底上形成端子，并且形成与本征基底并列布置在基底上的非本征基底。 本征基极和端子分别由第一和第二半导体材料构成。