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    Extrinsic base doping for bipolar junction transistors
    1.
    发明授权
    Extrinsic base doping for bipolar junction transistors 有权

    公开(公告)号：US10784346B2

    公开(公告)日：2020-09-22

    申请号：US16516815

    申请日：2019-07-19

    申请人： International Business Machines Corporation

    发明人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu

    IPC分类号： H01L29/10 ,  H01L21/225 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/732

    摘要： A method includes forming a base layer on a top surface of a substrate. A dielectric layer is formed on exposed surfaces of the base layer. A hardmask layer is formed on the base layer and the dielectric layer. A pattern is formed from the hardmask with a first opening and a second opening. Portions of a dielectric layer are removed from the top surface of the base layer at positions consistent with the pattern of the first opening and the second opening to form exposed surfaces defined as a first window and a second window in the dielectric layer. Deposits of a dopant-containing layer are limited on the exposed surfaces of: a first portion on the top surface of the base layer inside of the first window, and a second portion on the top surface of the base layer inside of the second window.

    Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage
    5.
    发明授权
    Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage 有权
    应力增强LDMOS晶体管，以最小化导通电阻并保持高击穿电压

    公开(公告)号：US09034712B2

    公开(公告)日：2015-05-19

    申请号：US14044163

    申请日：2013-10-02

    申请人： International Business Machines Corporation

    发明人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed H. Rankin ,  Yun Shi

    IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

    CPC分类号： H01L29/66492 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7843

    摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

    摘要翻译： 横向扩散金属氧化物半导体场效应晶体管（LDMOS晶体管）采用增强载流子迁移率（即导通电流）的应力层，同时还保持器件的高击穿电压。 由于漂移区域的掺杂浓度的增加被最小化，因此保持高的击穿电压。 在相邻的衬底中形成阱区和漂移区。 第一浅沟槽隔离（STI）区域形成在阱区域上并与阱区域相邻，并且第二STI区域形成在漂移区域上并与漂移区域相邻。 应力层沉积在LDMOS晶体管和第二STI区域中，第二STI区域根据应力层的极性将压缩或拉伸应力传播到漂移区域。 应力层的一部分可以在栅极上去除以改变栅极下方的反转区域中的应力极性。

    Heterojunction bipolar transistors with reduced parasitic capacitance
    7.
    发明授权
    Heterojunction bipolar transistors with reduced parasitic capacitance 有权
    具有降低的寄生电容的异质结双极晶体管

    公开(公告)号：US08957456B1

    公开(公告)日：2015-02-17

    申请号：US13955382

    申请日：2013-07-31

    申请人： International Business Machines Corporation

    发明人： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

    IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L21/20 ,  H01L29/737 ,  G06F17/50

    CPC分类号： H01L29/737 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/7378

    摘要： Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

    摘要翻译： 异质结双极晶体管的制造方法，器件结构和设计结构。 在半导体衬底中形成沟槽隔离区和集电极。 收集器与沟槽隔离区域共同延伸。 形成第一半导体层，其包括设置在集电极和沟槽隔离区上的单晶部分。 形成第二半导体层，其包括设置在第一半导体层的单晶部分上并具有覆盖在沟槽隔离区域上的外边缘的单晶部分。 第一半导体层的截面具有大于集电体的第一宽度的第二宽度。 第二半导体层的截面具有大于第二宽度的第三宽度。 空腔从第二半导体层的截面的外边缘横向延伸到第一半导体层的部分。

    NOTCH FILTER STRUCTURE WITH OPEN STUBS IN SEMICONDUCTOR SUBSTRATE AND DESIGN STRUCTURE
    9.
    发明申请
    NOTCH FILTER STRUCTURE WITH OPEN STUBS IN SEMICONDUCTOR SUBSTRATE AND DESIGN STRUCTURE 有权
    半导体基板和设计结构中的开孔晶体滤波器结构

    公开(公告)号：US20140203894A1

    公开(公告)日：2014-07-24

    申请号：US13748048

    申请日：2013-01-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Renata Camillo-Castillo ,  Hanyi Ding ,  Anthony K. Stamper

    IPC分类号： H01P1/203 ,  G06F17/50

    CPC分类号： H01P1/2039 ,  G06F17/5036 ,  G06F17/5045

    摘要： On-chip millimeter wave (mmW) notch filters with via stubs, methods of manufacture and design structures are disclosed. The notch filter includes a signal line comprising a metal trace line connected to a metal via stub partially extending into a semiconductor substrate. The notch filter further includes a defected ground plane connected to at least one or more additional metal via stubs partially extending into the semiconductor substrate.

    摘要翻译： 公开了具有通孔短片的片上毫米波（mmW）陷波滤波器，制造方法和设计结构。 陷波滤波器包括信号线，该信号线包括连接到部分延伸到半导体衬底中的金属通孔短截线的金属迹线。 陷波滤波器还包括连接到部分延伸到半导体衬底中的经由短截线的至少一个或多个附加金属的缺陷接地平面。

    Heterojunction bipolar transistors with an airgap between the extrinsic base and collector
    10.
    发明授权
    Heterojunction bipolar transistors with an airgap between the extrinsic base and collector 有权
    异质结双极晶体管，在外部基极和集电极之间具有气隙

    公开(公告)号：US09159817B2

    公开(公告)日：2015-10-13

    申请号：US14083769

    申请日：2013-11-19

    申请人： International Business Machines Corporation

    发明人： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

    IPC分类号： H01L29/66 ,  H01L29/73 ,  H01L29/737

    CPC分类号： H01L29/7371 ,  H01L29/0649 ,  H01L29/66242

    摘要： Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.

    摘要翻译： 异质结双极晶体管的制造方法，器件结构和设计结构。 在半导体衬底中形成集电极，在半导体衬底上形成本征基极，在本征基底上形成非本征基极。 气隙垂直位于外部基极和收集器之间。 接触表面位于气隙附近。 接触表面与收集器结合。 间隔件横向位于气隙和子集电极接触表面之间。