公开(公告)号：US20160379114A1

公开(公告)日：2016-12-29

申请号：US15262958

申请日：2016-09-12

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes

IPC: G06N3/08 ,  G06N3/063

CPC classification number: G06N3/08 ,  G06K9/00986 ,  G06N3/063

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

公开(公告)号：US20160371215A1

公开(公告)日：2016-12-22

申请号：US15257677

申请日：2016-09-06

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit S. Bains

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

Abstract translation: 装置可以包括被配置为从处理器接收数据流的第一部分的第一状态机引擎和被配置为从处理器接收数据流的第二部分的第二状态机引擎。 该装置包括缓冲器接口，该缓冲器接口被配置为使能第一和第二状态机引擎之间的数据传输。 缓冲器接口包括耦合到第一和第二状态机引擎的接口数据总线。 缓冲器接口被配置为在第一和第二状态机引擎之间提供数据。

公开(公告)号：US20160217365A1

公开(公告)日：2016-07-28

申请号：US15090305

申请日：2016-04-04

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06N3/04

CPC classification number: G06N3/04 ,  G05B19/045 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/02

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

Abstract translation: 具有程序缓冲器的状态机引擎。 程序缓冲器被配置为经由总线接口接收用于配置状态机格子的配置数据。 状态机引擎还包括配置为经由总线接口向外部设备提供修复地图数据的修复地图缓冲器。 状态机格子包括多个可编程元件。 每个可编程元件包括配置成分析数据并输出分析结果的多个存储器单元。

公开(公告)号：US20160188346A1

公开(公告)日：2016-06-30

申请号：US15063230

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes

IPC: G06F9/44

CPC classification number: G06F9/444 ,  G06F8/45 ,  G06F9/4498 ,  G06K9/00986

Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate.

公开(公告)号：US09280329B2

公开(公告)日：2016-03-08

申请号：US14329586

申请日：2014-07-11

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F9/45 ,  G06F9/44 ,  G06F9/00 ,  G06K9/00

CPC classification number: G06F9/444 ,  G06F8/45 ,  G06F9/4498 ,  G06K9/00986

Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate.

Abstract translation: 一种包括包括多个存储单元的数据分析单元的设备。 存储器单元分析数据流的至少一部分并输出分析结果。 该装置还包括检测单元。 检测单元包括与门。 与门接收分析结果作为第一输入。 检测单元还包括D触发器，其包括耦合到与门的第二输入的输出。

公开(公告)号：US20150277907A1

公开(公告)日：2015-10-01

申请号：US14736052

申请日：2015-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David R. Brown

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3005 ,  G05B19/045 ,  G06F9/3834

Abstract: State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error.

Abstract translation: 公开了国家机器引擎，包括具有指令插入寄存器的引擎。 一个这样的指令插入寄存器可以提供初始化指令，例如准备用于数据分析的状态机引擎。 指令插入寄存器还可以提供尝试解决在状态机引擎的操作期间发生的错误的指令。 指令插入寄存器也可以用于调试状态机引擎，例如在状态机经历致命错误之后。

公开(公告)号：US09135984B2

公开(公告)日：2015-09-15

申请号：US14133272

申请日：2013-12-18

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy ,  David R. Brown

IPC: G11C7/00 ,  G11C11/4093 ,  G11C7/10

CPC classification number: G11C11/4093 ,  G11C7/1009

Abstract: Disclosed are apparatuses and methods for writing data to a memory array of a buffer. One such apparatus may include a multiplexer that receives data words and a data mask. The multiplexer may change the order of the data words to group masked data words together and to group unmasked data words together. The multiplexer may also change the order of the data mask to group masking bits together and to group unmasking bits together. The apparatus may use the data words with the changed order and the data mask with the changed order to write data to the memory array.

Abstract translation: 公开了将数据写入缓冲器的存储器阵列的装置和方法。 一种这样的装置可以包括接收数据字和数据掩码的多路复用器。 复用器可以将数据字的顺序改变为将屏蔽的数据字组合在一起，并将未屏蔽的数据字组合在一起。 多路复用器还可以将数据掩码的顺序改变为组屏蔽位在一起，并且将未屏蔽位组合在一起。 设备可以使用具有改变顺序的数据字和具有改变顺序的数据掩码将数据写入存储器阵列。

公开(公告)号：US09118327B2

公开(公告)日：2015-08-25

申请号：US14087973

申请日：2013-11-22

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

IPC: G05B19/045 ,  G06F7/00 ,  G06F3/037 ,  H03K19/0175 ,  H03K19/20 ,  G06F17/50

CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

公开(公告)号：US20140204956A1

公开(公告)日：2014-07-24

申请号：US14223507

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes ,  Irene Junjuan Xu ,  Paul Glendenning

IPC: G06K9/00 ,  H04L12/883

CPC classification number: G06F13/1673 ,  G06F9/4498 ,  G06F13/124 ,  G06F13/4022 ,  G06F13/4282 ,  G06F17/30516 ,  G06K9/00496 ,  G06K9/00973 ,  G06K9/00979 ,  H04L49/9021

Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.

Abstract translation: 设备包括路由缓冲区。 路由缓冲器包括被配置为接收与数据流的至少一部分的分析有关的信号的第一端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第一路由线的第二端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第二路由选择线的第三端口。