公开(公告)号：US11735255B2

公开(公告)日：2023-08-22

申请号：US17880804

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Ferdinando Bedeschi ,  Paolo Fantini

IPC: G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0026 ,  G11C13/00 ,  G11C13/003 ,  G11C13/0004 ,  H10N70/066 ,  H10N70/231 ,  H10N70/882

Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally, or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).

公开(公告)号：US11715508B2

公开(公告)日：2023-08-01

申请号：US17387301

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Suryanarayana B. Tatapudi ,  Huy T. Vo ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G11C11/4094 ,  G11C11/4091

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/4091 ,  G11C11/4094

Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.

公开(公告)号：US11705211B2

公开(公告)日：2023-07-18

申请号：US17415646

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C29/52

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/22 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/52

Abstract: The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.

公开(公告)号：US11694748B2

公开(公告)日：2023-07-04

申请号：US17716716

申请日：2022-04-08

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0045

Abstract: A method, a circuit, and a system for reading memory cells. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.

公开(公告)号：US11646070B2

公开(公告)日：2023-05-09

申请号：US17499492

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221

Abstract: Methods, systems, and devices for memory cell sensing using an averaged reference voltage are described. A memory device may generate the averaged reference voltage that is specific to operating conditions or characteristics. The averaged reference voltage thus may track variations in cell use and cell characteristics. The memory device may generate the averaged reference voltage by shorting together reference nodes to determine an average of values associated with the reference nodes. The reference nodes may be associated with a codeword, which may store values corresponding to the reference nodes. The codeword may be balanced or nearly balanced to include equal or nearly equal quantities of different logic values.

公开(公告)号：US11538526B2

公开(公告)日：2022-12-27

申请号：US17162693

申请日：2021-01-29

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C14/00

Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

公开(公告)号：US11527279B2

公开(公告)日：2022-12-13

申请号：US16908299

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G06F11/30 ,  G11C11/22 ,  G06F11/07

Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

公开(公告)号：US11514969B2

公开(公告)日：2022-11-29

申请号：US17381996

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Ferdinando Bedeschi ,  Suryanarayana B. Tatapudi ,  Hyunyoo Lee ,  Adam S. El-Mansouri

IPC: G11C11/22

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

公开(公告)号：US11508455B1

公开(公告)日：2022-11-22

申请号：US17343348

申请日：2021-06-09

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C7/00 ,  G11C29/42 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/44

Abstract: Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.

公开(公告)号：US20220328087A1

公开(公告)日：2022-10-13

申请号：US17420976

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a selection line to selectively couple the memory cell with a digit line. The selection line may be provided in parallel to each digit line for multiplexing the digit lines toward a sense amplifier while a plurality of drivers, one for each selection line, may be provided in a staggered configuration under the memory array and split in even drivers and odd drivers for corresponding adjacent tiles of the memory array.