公开(公告)号：US20210011767A1

公开(公告)日：2021-01-14

申请号：US16510526

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang

IPC: G06F9/50 ,  G06F3/06 ,  G06F12/02 ,  G06F9/30

Abstract: Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.

公开(公告)号：US20200212935A1

公开(公告)日：2020-07-02

申请号：US16235171

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ting Luo

IPC: H03M13/11 ,  G06F11/10

Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.

公开(公告)号：US10446237B1

公开(公告)日：2019-10-15

申请号：US16024316

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Jung Sheng Hoei ,  Harish Reddy Singidi ,  Ting Luo ,  Ankit Vashi

IPC: G11C16/10 ,  G11C16/34 ,  G11C7/04

Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.

公开(公告)号：US12210448B2

公开(公告)日：2025-01-28

申请号：US18037631

申请日：2022-09-01

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

IPC: G06F12/02

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

公开(公告)号：US12197743B2

公开(公告)日：2025-01-14

申请号：US17991408

申请日：2022-11-21

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Zhengang Chen

IPC: G06F3/06

Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.

公开(公告)号：US20240272832A1

公开(公告)日：2024-08-15

申请号：US18586207

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Alberto Sassara ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Luigi Esposito ,  Paolo Papa ,  Salvatore Del Prete ,  Xiangang Luo ,  Xiaolai Zhu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

公开(公告)号：US20240211168A1

公开(公告)日：2024-06-27

申请号：US18600269

申请日：2024-03-08

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064

Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.

公开(公告)号：US11989433B2

公开(公告)日：2024-05-21

申请号：US17464316

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Jianmin Huang ,  Xiangang Luo

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.

公开(公告)号：US11914490B2

公开(公告)日：2024-02-27

申请号：US17492220

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Jianmin Huang ,  Xiangang Luo ,  Ashutosh Malshe

IPC: G06F11/20 ,  G06F3/06 ,  G06F11/10

CPC classification number: G06F11/2094 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0673 ,  G06F11/1068 ,  G06F2201/82

Abstract: A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11899574B2

公开(公告)日：2024-02-13

申请号：US17965542

申请日：2022-10-13

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Qing Liang

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0873 ,  G06F12/1045 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0804 ,  G06F12/0873 ,  G06F12/1054 ,  G06F13/1668 ,  G06F2212/7201

Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.