公开(公告)号：US11232828B2

公开(公告)日：2022-01-25

申请号：US17171853

申请日：2021-02-09

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L29/78 ,  G11C11/4091 ,  G11C11/4094

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

公开(公告)号：US11094697B2

公开(公告)日：2021-08-17

申请号：US16183468

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C11/403 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US11062753B2

公开(公告)日：2021-07-13

申请号：US16921868

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US11023111B2

公开(公告)日：2021-06-01

申请号：US15966483

申请日：2018-04-30

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Patrick Mullarkey

IPC: G06F3/0484 ,  G06F3/00 ,  G06F16/29 ,  G06F16/70 ,  G06F16/54 ,  G06F16/904 ,  G06F16/74

Abstract: A system, apparatuses such as a non-transitory readable medium, and a method for generating a geospatial interactive composite web-based image map are disclosed. The system may be configured to receive, from a user device, a request for creating a geospatial interactive composite web-based image map for a selected region of map data displayed by the user device, select images responsive to the request corresponding to defined sub-regions within the selected region of the map data displayed by the user device, construct a collage for the geospatial composite web-based image map responsive to selecting the images, and transmit the collage to the user device for display thereon as an overlay to the map data.

公开(公告)号：US20210066272A1

公开(公告)日：2021-03-04

申请号：US16553448

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Charles L. Ingalls ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Scott J. Derner

IPC: H01L25/18 ,  G11C11/4091 ,  H01L23/528 ,  G11C11/408 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

公开(公告)号：US10930653B2

公开(公告)日：2021-02-23

申请号：US16418150

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/10 ,  H01L27/108 ,  G11C11/408 ,  H01L49/02 ,  G11C11/4097 ,  H01L29/08 ,  G11C11/4094 ,  G11C5/02 ,  G11C11/403 ,  G11C11/4091

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US10916295B2

公开(公告)日：2021-02-09

申请号：US16110349

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/24 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/4091 ,  H01L27/12 ,  H01L29/786 ,  H01L27/11507 ,  H01L27/11509

Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

公开(公告)号：US10854276B2

公开(公告)日：2020-12-01

申请号：US16105631

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4091 ,  G11C7/06 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108 ,  G11C5/02 ,  G11C7/18 ,  G11C8/16 ,  G11C11/4096

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US10600472B2

公开(公告)日：2020-03-24

申请号：US16105889

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Huy T. Vo ,  Patrick Mullarkey ,  Jeffrey P. Wright ,  Michael A. Shore

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

公开(公告)号：US20200075082A1

公开(公告)日：2020-03-05

申请号：US16543315

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner

IPC: G11C11/4091 ,  G11C11/408

Abstract: An example apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.