公开(公告)号：US06605546B1

公开(公告)日：2003-08-12

申请号：US09901699

申请日：2001-07-11

申请人： Ramkumar Subramanian ,  Wolfram Grundke ,  Bhanwar Singh ,  Christopher F. Lyons ,  Marina V. Plat

发明人： Ramkumar Subramanian ,  Wolfram Grundke ,  Bhanwar Singh ,  Christopher F. Lyons ,  Marina V. Plat

IPC分类号： H01L21302

CPC分类号： H01L21/76808

摘要： A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.

摘要翻译： 一种用于形成半导体器件的方法包括在半导体衬底上形成第一层。 通过第一层形成至少一个孔。 在至少一个孔中形成底部抗反射涂层（BARC）层。 执行第一次加热以将BARC层加热至流动温度。 执行第二次加热以将BARC层加热至硬化温度，使得BARC层硬化，其中硬化温度大于流动温度。 进行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的硬化的BARC层在蚀刻期间用作耐蚀刻层。 作为第二加热步骤的替代方案，BARC可以简单地硬化。 第一和第二加热可以在加热室内进行，而不去除半导体衬底。

公开(公告)号：US06589804B1

公开(公告)日：2003-07-08

申请号：US09904089

申请日：2001-07-12

申请人： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： H01L2100

CPC分类号： G01B11/0625

摘要： A system for regulating ON and/or ONO dielectric formation is provided. The system includes one or more light sources, each light source directing light to one or more oxide and/or nitride layers being deposited and/or formed on a wafer. Light reflected from the oxide and/or nitride layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The system also includes a plurality of oxide/nitride formers; each oxide/nitride former corresponding to a respective portion of the wafer and providing for ON and/or ONO formation thereon. The processor selectively controls the oxide/nitride formers to regulate oxide and/or nitride layer formation on the respective ON and/or ONO formations on the wafer.

摘要翻译： 提供了一种用于调节ON和/或ONO电介质形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个氧化物和/或氮化物层。 从氧化物和/或氮化物层反射的光被测量系统收集，该系统处理收集的光。 所收集的光指示晶片上各个氧化物和/或氮化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上相应氧化物和/或氮化物层的厚度和/或均匀性。 该系统还包括多个氧化物/氮化物成形器; 每个氧化物/氮化物成形器对应于晶片的相应部分并且在其上提供ON和/或ONO形成。 处理器选择性地控制氧化物/氮化物成形器以调节晶片上相应的ON和/或ONO形成上的氧化物和/或氮化物层的形成。

公开(公告)号：US06566655B1

公开(公告)日：2003-05-20

申请号：US09729449

申请日：2000-12-04

申请人： Bryan K. Choo ,  Bhanwar Singh ,  Sanjay K. Yedur

发明人： Bryan K. Choo ,  Bhanwar Singh ,  Sanjay K. Yedur

IPC分类号： H01J3728

CPC分类号： H01J37/28 ,  G01N23/2251 ,  H01J2237/1514 ,  H01J2237/24578 ,  H01J2237/2611 ,  H01J2237/2814

摘要： The present invention provides a system and method that facilitates measuring and imaging topographical features of a substrate, including lines and trenches having reentrant profiles. One aspect of the invention provides an electron microscope that simultaneously scans a substrate with two or more electron beams that are directed against the substrate with substantially differing angles of incidence. Secondary electrons resulting from the interaction of the substrate with the beams are detected by one or more secondary electron detectors. Each secondary electron detector may simultaneously receive secondary electrons resulting from the interaction of the substrate with two or more electron beams. In another of its aspects, the invention provides methods of analysis that permit the interpretation of such data to analyze critical dimensions and form images of the substrate. Critical dimensions that may be determined include feature heights and reentrant profile shapes. The topographical information provided is more complete than that of conventional SEM imaging and is obtained more rapidly than would be possible using multiple scans of a single electron beam.

摘要翻译： 本发明提供了一种便于测量和成像基底的形貌特征的系统和方法，包括具有折返轮廓的线和沟槽。 本发明的一个方面提供了一种电子显微镜，其同时以基本上不同的入射角度针对衬底的两个或更多个电子束扫描衬底。 由基板与光束的相互作用产生的二次电子被一个或多个二次电子检测器检测。 每个二次电子检测器可以同时接收由衬底与两个或更多个电子束的相互作用产生的二次电子。 在另一方面，本发明提供了分析方法，其允许解释这些数据以分析临界尺寸并形成基底的图像。 可能确定的关键尺寸包括特征高度和可重入的轮廓形状。 所提供的地形信息比常规SEM成像更完整，并且比使用单个电子束的多次扫描可能获得的地形信息更快。

公开(公告)号：US06562248B1

公开(公告)日：2003-05-13

申请号：US09817518

申请日：2001-03-26

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

IPC分类号： G01N2100

CPC分类号： G03F1/84 ,  G03F1/26

摘要： A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.

摘要翻译： 提供了一种用于在补偿相移掩模中监测和控制孔蚀刻的系统。 该系统包括一个或多个光源，每个光源将光引导到在掩模上蚀刻的一个或多个孔。 从孔径反射的光由测量系统收集，该系统处理所收集的光。 通过孔的光可以类似地由处理收集的光的测量系统收集。 收集的光指示掩模上的开口的深度和/或宽度。 测量系统向确定孔径深度和/或宽度的可接受性的处理器提供深度和/或宽度相关数据。 该系统还包括与掩模中的孔蚀刻相关联的多个蚀刻装置。 处理器选择性地控制蚀刻装置以调节孔径蚀刻。

公开(公告)号：US06562185B2

公开(公告)日：2003-05-13

申请号：US09955552

申请日：2001-09-18

申请人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

发明人： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC分类号： B24B3700

CPC分类号： B24B37/015

摘要： A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties. Such characterization can be employed, for example, to better understand a CMP process, to facilitate initializing subsequent chemical mechanical polishing processes and/or apparatus and/or to control such chemical mechanical polishing processes and/or apparatus by monitoring and/or controlling wafer temperature.

摘要翻译： 提供了表征化学机械抛光工艺的系统。 该系统包括具有位于金属，多晶硅和/或电介质层和/或衬底中和/或上的金属，多晶硅和/或电介质层和/或衬底和温度传感器的晶片。 该系统还包括一个温度监控系统，可以从温度传感器读取晶圆温度，并且可以分析晶圆温度以表征化学机械抛光过程。 这种表征包括产生关于晶片温度和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。 这些关系与晶片温度相关，如与抛光时间，压力，速度，浆料性质和晶片/金属层性质等参数相关。 可以采用这种表征，例如，更好地理解CMP工艺，以便于初始化随后的化学机械抛光工艺和/或设备和/或通过监测和/或控制晶片温度来控制这种化学机械抛光工艺和/或设备 。

公开(公告)号：US06545273B1

公开(公告)日：2003-04-08

申请号：US09729292

申请日：2000-12-04

申请人： Bhanwar Singh ,  Bharath Rangarajan ,  Sanjay K. Yedur

发明人： Bhanwar Singh ,  Bharath Rangarajan ,  Sanjay K. Yedur

IPC分类号： G01N2300

CPC分类号： G01Q40/00 ,  Y10S977/874

摘要： The present invention comprises a system for deconvolving tip effects associated with scanning tips in scanning probe microscopes and other scanning systems. The system comprises a scanning system operable to scan a feature or artifact with multiple, different type scanning tips and generate scan data associated therewith and a processor operably coupled to the scanning system. The processor is adapted to determine characteristics associated with the multiple, different type scanning tips using the scan data associated therewith. The present invention also comprises a method of determining scanning probe microscope tip effects. The method comprises the steps of scanning a feature or artifact with a plurality of different type scanning tips, resulting in a plurality of scan data sets associated with the different type scanning tips. The tip effects associated with the different type scanning tips are then deconvolved using the plurality of scan data sets.

摘要翻译： 本发明包括一种用于在扫描探针显微镜和其它扫描系统中与扫描尖端相关联的尖端效应的去卷积的系统。 该系统包括扫描系统，其可操作以用多个不同类型的扫描尖端扫描特征或伪像，并且生成与其相关联的扫描数据和可操作地耦合到扫描系统的处理器。 处理器适于使用与其相关联的扫描数据来确定与多个不同类型扫描尖端相关联的特性。 本发明还包括确定扫描探针显微镜尖端效应的方法。 该方法包括以多个不同类型扫描尖端扫描特征或伪影的步骤，导致与不同类型的扫描尖端相关联的多个扫描数据集。 然后使用多个扫描数据集对与不同类型的扫描尖端相关联的尖端效应进行去卷积。

公开(公告)号：US06534418B1

公开(公告)日：2003-03-18

申请号：US09845656

申请日：2001-04-30

申请人： Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

发明人： Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

IPC分类号： H01L21302

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/7833

摘要： An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.

摘要翻译： 使用含硅成像层来限定次分辨率门结构的示例性方法可以包括在多晶硅层上沉积抗反射涂层，在抗反射涂层上沉积成像层，选择性地蚀刻抗反射涂层以形成 使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。 因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用修剪蚀刻技术，而不会有抗蚀剂侵蚀或高宽比图案崩溃的风险。 这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

公开(公告)号：US06528398B1

公开(公告)日：2003-03-04

申请号：US09775084

申请日：2001-02-01

申请人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

发明人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

IPC分类号： H01L2176

CPC分类号： G03F7/094 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76816

摘要： An exemplary embodiment described in the disclosure relates to a method of fabricating an integrated circuit which includes providing a bulk layer over a semiconductor substrate, providing an imaging layer over the bulk layer, imaging the imaging layer to expose portions of the imaging layer, removing the exposed portions of the imaging layer, etching the bulk layer at locations where exposed portions of the imaging layer were removed to provide at least one aperture in the bulk layer, and silylating the bulk layer.

摘要翻译： 本公开中描述的示例性实施例涉及一种制造集成电路的方法，其包括在半导体衬底上提供体层，在体层上提供成像层，使成像层成像以暴露成像层的部分，去除 成像层的暴露部分，在去除成像层的暴露部分的位置处蚀刻体层以在本体层中提供至少一个孔，以及使体层甲硅烷化。

公开(公告)号：US06514867B1

公开(公告)日：2003-02-04

申请号：US09817586

申请日：2001-03-26

申请人： Angela T. Hui ,  Bhanwar Singh

发明人： Angela T. Hui ,  Bhanwar Singh

IPC分类号： H01L2100

CPC分类号： H01L21/31144

摘要： An exemplary method is described which forms narrow trench lines having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a trench line is to be formed; etching the hard mask with a first critical dimension at the top of the hard mask and a second critical dimension at the bottom of the hard mask; and etching a trench line using the hard mask to transfer the second critical dimension to the trench line.

摘要翻译： 描述了一种示例性的方法，其形成具有小于使用常规光刻技术的临界尺寸的临界尺寸的窄沟槽线。 该方法可以包括在要形成沟槽线的材料层上提供硬掩模; 在硬掩模的顶部以第一临界尺寸蚀刻硬掩模，在硬掩模的底部蚀刻第二临界尺寸; 以及使用所述硬掩模蚀刻沟槽线以将所述第二临界尺寸转移到所述沟槽线。

公开(公告)号：US06514849B1

公开(公告)日：2003-02-04

申请号：US09824420

申请日：2001-04-02

申请人： Angela T. Hui ,  Bhanwar Singh

发明人： Angela T. Hui ,  Bhanwar Singh

IPC分类号： H01L214763

CPC分类号： H01L21/31144

摘要： An exemplary method of forming contact holes includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.

摘要翻译： 形成接触孔的示例性方法包括在抗反射涂层（ARC）层上提供光致抗蚀剂图案，其中ARC层沉积在材料层上; 根据光致抗蚀剂图案蚀刻ARC层以形成ARC特征; 在ARC特征的侧面上形成间隔物; 并且使用间隔物和ARC特征蚀刻沟槽线作为硬掩模以限定蚀刻的材料层的部分。