公开(公告)号：US20170358678A1

公开(公告)日：2017-12-14

申请号：US15665395

申请日：2017-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

公开(公告)号：US09799651B2

公开(公告)日：2017-10-24

申请号：US15074986

申请日：2016-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/76802 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.

公开(公告)号：US20170256444A1

公开(公告)日：2017-09-07

申请号：US15062226

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/768 ,  H01L29/423 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/76834 ,  H01L21/02123 ,  H01L21/76802 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a first dielectric layer, a shielding layer and a connector. The first gate stack is over a substrate. The first dielectric layer is aside the first gate stack, wherein the top surface of the first gate stack is lower than the top surface of the first dielectric layer such that a first recess is provided above the first gate stack. The shielding layer is on the surface of the first recess and extends onto the top surface of the first dielectric layer. The connector is through the shielding layer and is electrically connected to the first gate stack.

公开(公告)号：US20170229452A1

公开(公告)日：2017-08-10

申请号：US15071224

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, a first gate, a second gate, an opening and a first dielectric layer. The substrate includes a first semiconductor fin, a second semiconductor fin and a trench between the first semiconductor fin and the second semiconductor fin. The insulator is disposed in the trench. The first gate is disposed on the first semiconductor fin. The second gate is disposed on the second semiconductor fin. The opening is disposed between the first gate and the second gate. The first dielectric layer is disposed in the opening to electrically insulate the first gate and the second gate, wherein the first dielectric layer includes an air gap therein.

公开(公告)号：US09716154B2

公开(公告)日：2017-07-25

申请号：US15051619

申请日：2016-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/41 ,  H01L29/40 ,  H01L29/417 ,  H01L21/311

CPC classification number: H01L29/4991 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/515 ,  H01L2221/1042

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one source drain structure, at least one bottom conductor, and a first dielectric layer. The first gate structure is present on the substrate. The source drain structure is present on the substrate. The bottom conductor is electrically connected to the source drain structure. The bottom conductor has an upper portion and a lower portion between the upper portion and the source drain structure, and a gap is at least present between the upper portion of the bottom conductor and the first gate structure. The first dielectric layer is at least present between the lower portion of the bottom conductor and the first gate structure.

公开(公告)号：US20170200821A1

公开(公告)日：2017-07-13

申请号：US14990797

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L21/308 ,  H01L23/535 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L21/3085 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795

Abstract: Contact structures, FinFET devices and methods of forming the same are disclosed. One of the contact structures includes a source/drain region, a mask layer, a connector and a shielding pattern. The source/drain region is between two gate stacks. A mask layer is over the gate stacks and has an opening corresponding to the source/drain region. The connector is electrically connected to the source/drain region, penetrates through the opening of the mask layer and protrudes above and below the mask layer. The shielding pattern is between the mask layer and the connector and in physical contact with the mask layer.

公开(公告)号：US09704752B1

公开(公告)日：2017-07-11

申请号：US15054141

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a fin field effect transistor (FinFET) comprising the following steps is provided. A substrate comprising a plurality of trenches and a plurality of semiconductor fins between the trenches is provided. A plurality of insulators are formed in the trenches. A fin cut process is performed to remove portions of the semiconductor fins until a plurality of concaves are formed between the insulators. A gate stack is formed to partially cover the semiconductor fins and the insulators.

公开(公告)号：US09704751B1

公开(公告)日：2017-07-11

申请号：US15054138

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886

Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until concaves are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

公开(公告)号：US20170170316A1

公开(公告)日：2017-06-15

申请号：US14968920

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L23/535 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: In accordance with some embodiments of the present disclosure, a fin-FET device includes a substrate, a stack structure, a source and drain region, a sidewall insulator and a metal connector. The stack structure including a gate stack is disposed on the substrate. The source and drain region is disposed beside the stack structure. The sidewall insulator is disposed on the source and drain region. The sidewall insulator includes a bottom portion and an upper portion. An interface is formed between the bottom portion and the upper portion and the bottom portion is located between the upper portion and the source and drain region. The metal connector stacks on the source and drain region and the sidewall insulator is located between the metal connector and the stack structure.

公开(公告)号：US09627316B1

公开(公告)日：2017-04-18

申请号：US14968921

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L29/423 ,  H01L21/02 ,  H01L23/538 ,  H01L23/482

CPC classification number: H01L23/528 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/4821 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5381 ,  H01L29/4232

Abstract: A field effect transistor comprising a substrate, at least one gate stack structure, source and drain regions and an interconnect structure is described. The interconnect structure comprises a metal interconnect connected to a conductive region, an adhesion sheath structure and a cap layer. The adhesion sheath structure is disposed between the metal interconnect and inter-dielectric layers and surrounds the metal interconnect. The cap layer is disposed on the metal interconnect and covers a gap between the metal interconnect and the inter-dielectric layer.