公开(公告)号：US20180350948A1

公开(公告)日：2018-12-06

申请号：US16050094

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Han-Wen Liao ,  Xuan-You Yan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L21/32135 ,  H01L21/32137 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

公开(公告)号：US10074547B2

公开(公告)日：2018-09-11

申请号：US14135017

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Shu Tseng ,  You-Feng Chen ,  Yen-Yu Chen

IPC: H01L21/67

CPC classification number: H01L21/6715

Abstract: Embodiments of a photoresist supply system including a photoresist nozzle device are provided. The photoresist nozzle device includes a tube including a first segment, a curved segment connected to the first segment, and a second segment connected to the curved segment. The photoresist nozzle device also includes a nozzle connected to the second segment.

公开(公告)号：US09803274B2

公开(公告)日：2017-10-31

申请号：US14080561

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei Bih ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Hsien-Chieh Hsiao ,  Chang-Sheng Lee ,  Wei-Chen Liao ,  Wei Zhang

IPC: C23C14/35 ,  C23C14/34 ,  H01J37/34 ,  H01J37/32 ,  C23C14/56

CPC classification number: C23C14/34 ,  C23C14/564 ,  H01J37/32467 ,  H01J37/32477 ,  H01J37/34 ,  H01J37/3411 ,  H01J37/3426 ,  H01J37/3447

Abstract: A physical vapor deposition (PVD) chamber, a process kit of a PVD chamber and a method of fabricating a process kit of a PVD chamber are provided. In various embodiments, the PVD chamber includes a sputtering target, a power supply, a process kit, and a substrate support. The sputtering target has a sputtering surface that is in contact with a process region. The power supply is electrically connected to the sputtering target. The process kit has an inner surface at least partially enclosing the process region, and a liner layer disposed on the inner surface. The substrate support has a substrate receiving surface, wherein the liner layer disposed on the inner surface of the process kit has a surface roughness (Rz), and the surface roughness (Rz) is substantially in a range of 50-200 μm.

公开(公告)号：US09685441B2

公开(公告)日：2017-06-20

申请号：US15376353

申请日：2016-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Wei Zhang

IPC: H01L29/51 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.

公开(公告)号：US09611546B2

公开(公告)日：2017-04-04

申请号：US15099687

申请日：2016-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Chien-Hao Tseng ,  Yen-Yu Chen ,  Ching-Chia Wu ,  Chang-Sheng Lee ,  Wei Zhang

IPC: H01L21/469 ,  C23C16/44 ,  H01L21/28 ,  C23C16/448 ,  C23C16/455 ,  H01L29/51

CPC classification number: C23C16/4402 ,  C23C16/4481 ,  C23C16/4485 ,  C23C16/45544 ,  C23C16/45553 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/28185 ,  H01L29/517

Abstract: A method for fabricating a semiconductor structure and a solid precursor delivery system for a semiconductor fabrication is provided, the method including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film.

公开(公告)号：US09425109B2

公开(公告)日：2016-08-23

申请号：US14292162

申请日：2014-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen ,  Chang-Sheng Lee ,  Wei Zhang

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/67 ,  H01L21/3105 ,  B24B37/013 ,  B24B49/12

CPC classification number: B24B37/013 ,  B24B49/12 ,  H01L21/28088 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/67075 ,  H01L22/12 ,  H01L22/26 ,  H01L29/66545 ,  H01L29/7851

Abstract: A planarization method is provided. The planarization method includes providing a wafer, in which the wafer includes a work function layer, a surface layer formed on the work function layer and oxidized from the work function layer, and a planarization layer disposed on or above the surface layer, performing a chemical-mechanical planarization (CMP) process on the planarization layer, providing an incident light to a surface of the wafer under the CMP process, detecting absorption of the incident light by the surface layer; and stopping the CMP process in response to an increase in the detected absorption of the incident light.

Abstract translation: 提供了一种平面化方法。 平面化方法包括提供晶片，其中晶片包括功函数层，形成在功函数层上并从功函数层氧化的表面层，以及设置在表层上或表面层上的平坦化层，执行化学 在平坦化层上的机械平面化（CMP）工艺，在CMP工艺下向晶片的表面提供入射光，检测由表面层吸收的入射光; 并且响应于检测到的入射光的吸收的增加而停止CMP处理。