公开(公告)号：US20060220674A1

公开(公告)日：2006-10-05

申请号：US11094810

申请日：2005-03-31

申请人： Evelina Yeung ,  Karthisha Canagasaby ,  Sanjay Dabral

发明人： Evelina Yeung ,  Karthisha Canagasaby ,  Sanjay Dabral

IPC分类号： H03K19/003

CPC分类号： H03K19/00323 ,  H03K19/018528

摘要： A pre-driver circuit includes a first stage to generate a first pre-driver signal and a second stage to generate a second pre-driver signal. The first and second stages are to generate the first and second pre-driver signals to cross at a point which reduces rise-and-fall mismatch in differential signal outputs from a current-mode driver.

摘要翻译： 预驱动器电路包括产生第一预驱动器信号的第一级和产生第二预驱动器信号的第二级。 第一和第二阶段是产生第一和第二预驱动器信号以在减少来自当前模式驱动器的差分信号输出的上升和下降失配的点处交叉。

公开(公告)号：US20060140320A1

公开(公告)日：2006-06-29

申请号：US11021953

申请日：2004-12-23

申请人： Richard Jensen ,  Dave Dunning ,  Sanjay Dabral

发明人： Richard Jensen ,  Dave Dunning ,  Sanjay Dabral

IPC分类号： H03D3/24

CPC分类号： H04L7/0337 ,  H03D13/004 ,  H04L7/0025 ,  H04L25/4908

摘要： An apparatus and method to improve bandwidth and reduce phase error in a tracking receiver is presented. According to one embodiment, an apparatus is presented comprising a phase comparator to generate indications based on a phase of a local clock signal and transitions in a stream of received data, an electoral loop filter to generate a phase shift signal based on the indications received from the phase comparator in a time interval, and a local clock controller to adjust the local clock signal based on the signal asserted from the electoral loop filter. The phase shift signal is either a phase increment signal or a phase decrement signal that is issued according to the majority of either increment indications or decrement indications received during the time interval.

摘要翻译： 提出了一种改善跟踪接收机带宽并减少相位误差的装置和方法。 根据一个实施例，提供了一种装置，其包括相位比较器，用于基于本地时钟信号的相位和接收数据流中的转换来产生指示，选通环路滤波器，基于从 相位比较器在时间间隔内，本地时钟控制器根据从选通环路滤波器断言的信号来调整本地时钟信号。 相移信号是根据在时间间隔期间接收到的增量指示或递减指示的大部分发出的相位增量信号或相位递增信号。

公开(公告)号：US20060067066A1

公开(公告)日：2006-03-30

申请号：US10950827

申请日：2004-09-27

申请人： Pascal Meier ,  Sanjay Dabral

发明人： Pascal Meier ,  Sanjay Dabral

IPC分类号： H01R12/28

CPC分类号： G06F1/189 ,  G06F1/184 ,  G06F1/185 ,  G06F1/186 ,  H01R12/79 ,  H05K1/14 ,  H05K1/147 ,  H05K3/222 ,  H05K3/305 ,  H05K2201/044 ,  H05K2201/10356 ,  H05K2201/10492 ,  H05K2201/10704 ,  H05K2201/2027 ,  Y10T29/49117

摘要： A system and method are disclosed in which flex cables are affixed to PCBs, for providing high-speed signaling paths between ICs disposed upon the PCBs. The flex cables are fixably attached to the PCBs so as to substantially mimic their structural orientation. Where the configuration includes more than one PCB, the flex cables include multiple portions which are temporarily separable from one another and from the die, using flex-to-flex and flex-to-package connectors, allowing field maintenance of the configuration. By routing the high-speed signals between ICs onto the flex cable, single-layer PCBs can be used for non-critical and power delivery signals, at substantial cost savings. By disposing the flex cables onto the PCB rather than allowing the cables to float freely, the configuration is thermally managed as if the signals were on the PCB and cable routing problems are avoided.

公开(公告)号：US20060018265A1

公开(公告)日：2006-01-26

申请号：US10897609

申请日：2004-07-23

申请人： Tim Frodsham ,  Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Theodore Schoenborn ,  Lakshminarayan Krishnamurty

发明人： Tim Frodsham ,  Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Theodore Schoenborn ,  Lakshminarayan Krishnamurty

IPC分类号： H04L12/26

CPC分类号： H04L43/50 ,  H04L41/082 ,  H04L69/40

摘要： A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave agent's transmitter and receiver are independently controlled and the master agent may use a slave-echoed data test pattern to detect errors and subsequently sets the appropriate status bits in a loop back status register

摘要翻译： 用于测试分层接口的通信链路的环回测试，其中主代理程序使用环回控制寄存器编程用于从属代理的电参数，例如偏移，定时和电流补偿。 从属代理的发送器和接收器是独立控制的，主代理可以使用从属回波数据测试模式来检测错误，并随后在循环状态寄存器中设置适当的状态位

公开(公告)号：US06977537B2

公开(公告)日：2005-12-20

申请号：US10890332

申请日：2004-07-13

申请人： Santanu Chaudhuri ,  Sanjay Dabral ,  Karthisha Canagasaby

发明人： Santanu Chaudhuri ,  Sanjay Dabral ,  Karthisha Canagasaby

IPC分类号： H03D3/00 ,  H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/18

CPC分类号： H03L7/0898 ,  H03L7/095 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18 ,  Y10S331/02

摘要： According to some embodiments, a low gain phase-locked loop circuit is provided.

摘要翻译： 根据一些实施例，提供了一种低增益锁相环电路。

公开(公告)号：US20050262184A1

公开(公告)日：2005-11-24

申请号：US10850856

申请日：2004-05-21

申请人： Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Tim Frodsham ,  Theodore Schoenborn

发明人： Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Tim Frodsham ,  Theodore Schoenborn

IPC分类号： G06F15/16

CPC分类号： G06F13/4273

摘要： A method and apparatus for advancing initialization messages in a lock-step manner when initializing an interface is presented. In one embodiment, a lane receiver may transition to a receiver ready attribute when a given number of current training sequence messages is correctly received. When the receiver ready attributes of all the lanes are set, a local acknowledgement attribute may be set. Similarly, a lane receiver may transition to a remote acknowledgement attribute when a given number of current training sequence messages with acknowledgement field set is correctly received. When both the local acknowledgement attribute and the remote acknowledgement attribute are set, the port may advance to the next training sequence messages.

摘要翻译： 提出了一种在初始化界面时以锁步方式推进初始化消息的方法和装置。 在一个实施例中，当正确地接收到给定数量的当前训练序列消息时，车道接收器可以转换到接收器就绪属性。 当所有通道的接收器就绪属性被设置时，可以设置本地确认属性。 类似地，当正确地接收到具有确认字段集的给定数量的当前训练序列消息时，通道接收器可以转换到远程确认属性。 当本地确认属性和远程确认属性都被设置时，端口可以前进到下一个训练序列消息。

公开(公告)号：US20050259696A1

公开(公告)日：2005-11-24

申请号：US10850809

申请日：2004-05-21

申请人： Maurice Steinman ,  Rahul Shah ,  Naveen Cherukuri ,  Aaron Spink ,  Allen Baum ,  Sanjay Dabral ,  Tim Frodsham ,  David Dunning ,  Theodore Schoenborn

发明人： Maurice Steinman ,  Rahul Shah ,  Naveen Cherukuri ,  Aaron Spink ,  Allen Baum ,  Sanjay Dabral ,  Tim Frodsham ,  David Dunning ,  Theodore Schoenborn

IPC分类号： G06F13/38 ,  G06F13/40 ,  H04L12/26 ,  H04L12/28 ,  H04L29/08

CPC分类号： G06F13/4018 ,  G06F13/4009 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

摘要翻译： 本发明的实施例提供了一种用于将链路划分成一个或多个缩小宽度链路的算法。 对于本发明的一个实施例，采用复用方案来实现特定循环冗余校验所需的位传输顺序。 多路复用的输出位随后在芯片上转动，以减少车载路由拥塞。

公开(公告)号：US20050099219A1

公开(公告)日：2005-05-12

申请号：US11014093

申请日：2004-12-15

申请人： Sanjay Dabral ,  Santanu Chaudhuri

发明人： Sanjay Dabral ,  Santanu Chaudhuri

IPC分类号： H03K19/173 ,  H03L5/00

CPC分类号： H03K19/1732

摘要： A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.

公开(公告)号：US06788155B2

公开(公告)日：2004-09-07

申请号：US10334276

申请日：2002-12-31

申请人： Santanu Chaudhuri ,  Sanjay Dabral ,  Karthisha Canagasaby

发明人： Santanu Chaudhuri ,  Sanjay Dabral ,  Karthisha Canagasaby

IPC分类号： H03L700

CPC分类号： H03L7/0898 ,  H03L7/095 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18 ,  Y10S331/02

摘要： A low gain phase-locked loop circuit comprising a phase detector, a plurality of voltage controlled oscillators, wherein each voltage controlled oscillator is selectable to provide an output clock signal based at least in part on information generated by the phase detector; and a multiplexer to output a signal generated by one of the voltage controlled oscillators as the output clock signal based on a multi-bit selection control signal.

摘要翻译： 一种低增益锁相环电路，包括相位检测器，多个压控振荡器，其中每个压控振荡器可选地至少部分地基于由相位检测器产生的信息来提供输出时钟信号; 以及多路复用器，其基于多位选择控制信号，输出由所述压控振荡器之一产生的信号作为所述输出时钟信号。

公开(公告)号：US06704277B1

公开(公告)日：2004-03-09

申请号：US09474564

申请日：1999-12-29

申请人： Sanjay Dabral ,  Ming Zeng ,  Chung-Wai Yue

发明人： Sanjay Dabral ,  Ming Zeng ,  Chung-Wai Yue

IPC分类号： H04J100

CPC分类号： G01R31/001 ,  H04B3/487

摘要： In an electronic system having logic agents that communicate with each other through one or more signal lines, a method for testing high speed digital signaling on the signal lines is disclosed. The method involves sensing a first crosstalk signal induced by a first digital signal. The first digital signal is driven by a first logic agent into a signal line to communicate with a second agent. The second agent is coupled to receive the first digital signal from the signal line. A logic waveform that represents the digital signal is recorded and/or displayed, based upon the crosstalk signal. The technique may also be used for testing simultaneous bidirectional signaling on the same signal line.

摘要翻译： 在具有通过一个或多个信号线彼此通信的逻辑代理的电子系统中，公开了一种用于在信号线上测试高速数字信令的方法。 该方法包括感测由第一数字信号引起的第一串扰信号。 第一数字信号由第一逻辑代理驱动到信号线中以与第二代理进行通信。 第二代理被耦合以从信号线接收第一数字信号。 基于串扰信号，记录和/或显示表示数字信号的逻辑波形。 该技术还可用于测试同一信号线上的同步双向信令。