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    Mechanism to adjust a clock signal based on embedded clock information
    1.
    发明申请
    Mechanism to adjust a clock signal based on embedded clock information 审中-公开
    基于嵌入式时钟信息调整时钟信号的机制

    公开(公告)号：US20060140320A1

    公开(公告)日：2006-06-29

    申请号：US11021953

    申请日：2004-12-23

    申请人： Richard Jensen ,  Dave Dunning ,  Sanjay Dabral

    发明人： Richard Jensen ,  Dave Dunning ,  Sanjay Dabral

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0337 ,  H03D13/004 ,  H04L7/0025 ,  H04L25/4908

    摘要： An apparatus and method to improve bandwidth and reduce phase error in a tracking receiver is presented. According to one embodiment, an apparatus is presented comprising a phase comparator to generate indications based on a phase of a local clock signal and transitions in a stream of received data, an electoral loop filter to generate a phase shift signal based on the indications received from the phase comparator in a time interval, and a local clock controller to adjust the local clock signal based on the signal asserted from the electoral loop filter. The phase shift signal is either a phase increment signal or a phase decrement signal that is issued according to the majority of either increment indications or decrement indications received during the time interval.

    摘要翻译： 提出了一种改善跟踪接收机带宽并减少相位误差的装置和方法。 根据一个实施例，提供了一种装置，其包括相位比较器，用于基于本地时钟信号的相位和接收数据流中的转换来产生指示，选通环路滤波器，基于从 相位比较器在时间间隔内，本地时钟控制器根据从选通环路滤波器断言的信号来调整本地时钟信号。 相移信号是根据在时间间隔期间接收到的增量指示或递减指示的大部分发出的相位增量信号或相位递增信号。

    Phase/frequency detector for tracking receivers
    2.
    发明授权
    Phase/frequency detector for tracking receivers 有权
    用于跟踪接收器的相位/频率检测器

    公开(公告)号：US07474714B2

    公开(公告)日：2009-01-06

    申请号：US10334935

    申请日：2002-12-31

    申请人： Chamath Abhayagunawardhana ,  Dave Dunning ,  Sanjay Dabral ,  Ken Drottar

    发明人： Chamath Abhayagunawardhana ,  Dave Dunning ,  Sanjay Dabral ,  Ken Drottar

    IPC分类号： H04L27/00

    CPC分类号： H04L7/033

    摘要： A receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase. If certain meta-stable conditions are observed by the voter block, the voter block will vote in one direction in order to push the system out of the meta-stable condition.

    摘要翻译： 数字电子系统内的接收装置包括采样单元，选举块和本地时钟相位调整单元。 采样单元在三个时间点以一个位周期的一半的间隔对输入行进行采样。 采样单元将采样过程中获得的值传递给选举块。 选民块决定是否向本地时钟相位调整单位输出向上或向下的投票。 选举块通过上下控制信号与本地时钟相位调整单元进行通信。 本地时钟相位调整单元确定是否应调整本地时钟相位，如果是，是否提前或延迟本地时钟相位。 如果选民块观察到某些元稳定条件，则选民块将以一个方向投票，以将该制度推出元稳定状态。

    Input/output driver swing control and supply noise rejection
    3.
    发明授权
    Input/output driver swing control and supply noise rejection 有权
    输入/输出驱动器摆幅控制和电源噪声抑制

    公开(公告)号：US08143911B2

    公开(公告)日：2012-03-27

    申请号：US12060251

    申请日：2008-03-31

    申请人： Zuoguo Wu ,  Feng Chen ,  Sanjay Dabral

    发明人： Zuoguo Wu ,  Feng Chen ,  Sanjay Dabral

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/0175

    CPC分类号： H04L25/0276

    摘要： In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.

    摘要翻译： 通常，在一个方面，本公开描述了一种具有平均器以接收发射机的差分输出电压并产生平均发射机输出电压的装置。 比较器将平均发射机输出电压与参考电压进行比较，并产生它们之间的差值。 积分器将整合平均发射机输出电压和参考电压随时间的差异。 积分差值被反馈给发射机以偏置发射机。

    Circuit board including stubless signal paths and method of making same
    5.
    发明授权
    Circuit board including stubless signal paths and method of making same 有权
    电路板包括无铅信号路径及其制作方法

    公开(公告)号：US07907418B2

    公开(公告)日：2011-03-15

    申请号：US12628778

    申请日：2009-12-01

    申请人： Pascal Meier ,  Sanjay Dabral

    发明人： Pascal Meier ,  Sanjay Dabral

    IPC分类号： H05K7/00

    CPC分类号： H05K3/4611 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/024 ,  H05K1/112 ,  H05K1/147 ,  H05K3/0064 ,  H05K3/4084 ,  H05K2201/091 ,  H05K2201/09318 ,  H05K2201/10734 ,  Y10T29/49126

    摘要： A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

    摘要翻译： 电路板可以包括第一和第二侧，在侧面之间的多个电路板层和位于相应的电路板层中的多个信号迹线。 电路板层和信号迹线可以从电路板的第一侧的第一部件连接区域延伸到电路板的第一侧的第二部件连接区域。 因此，信号迹线可以在组件连接区域之间形成通过电路板的不连续的信号路径。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

    Method of fabricating a linearized output driver and terminator
    9.
    发明授权
    Method of fabricating a linearized output driver and terminator 有权
    制造线性化输出驱动器和终端器的方法

    公开(公告)号：US07250333B2

    公开(公告)日：2007-07-31

    申请号：US10394977

    申请日：2003-03-20

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L29/66659 ,  H01L29/7835 ,  Y02P80/30

    摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

    摘要翻译： 描述了用于线性化输出驱动器和终止器的方法和装置。 在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。 该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。 该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。 该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器 基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。

    Pre-drivers for current-mode I/O drivers
    10.
    发明授权
    Pre-drivers for current-mode I/O drivers 有权
    当前模式I / O驱动程序的前驱动程序

    公开(公告)号：US07245156B2

    公开(公告)日：2007-07-17

    申请号：US11094810

    申请日：2005-03-31

    申请人： Evelina F. Yeung ,  Karthisha Canagasaby ,  Sanjay Dabral

    发明人： Evelina F. Yeung ,  Karthisha Canagasaby ,  Sanjay Dabral

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/00323 ,  H03K19/018528

    摘要： A pre-driver circuit includes a first stage to generate a first pre-driver signal and a second stage to generate a second pre-driver signal. The first and second stages are to generate the first and second pre-driver signals to cross at a point which reduces rise-and-fall mismatch in differential signal outputs from a current-mode driver.

    摘要翻译： 预驱动器电路包括产生第一预驱动器信号的第一级和产生第二预驱动器信号的第二级。 第一和第二阶段是产生第一和第二预驱动器信号以在减少来自当前模式驱动器的差分信号输出的上升和下降失配的点处交叉。