公开(公告)号：US06974739B2

公开(公告)日：2005-12-13

申请号：US10440005

申请日：2003-05-16

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/768 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/8238

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11546

Abstract: A gate dielectric (150) for a gate (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate (140). The dielectric thickness on the other gate is controlled by the dopant concentration in the other gate. The gates may be gates of different MOS transistors, or a select gate and a floating gate of a memory cell. Other features are also provided.

Abstract translation: 用于栅极（160）的栅极电介质（150）通过热氧化同时作为另一栅极（140）的表面上的电介质形成。 另一个栅极上的电介质厚度由另一个栅极中的掺杂剂浓度控制。 栅极可以是不同MOS晶体管的栅极，或存储单元的选择栅极和浮置栅极。 还提供其他功能。

公开(公告)号：US20050180217A1

公开(公告)日：2005-08-18

申请号：US11101754

申请日：2005-04-08

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C11/34 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L29/788

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在具有多个浮动栅极（160）的存储单元（110）中，在浮置栅极之前形成选择栅极（140）。 在一些实施例中，存储器单元还具有在选择栅极之后形成的控制栅极（170）。 衬底隔离区（220）形成在半导体衬底（120）中。 衬底隔离区突出于衬底上方。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区露出。 在浮动栅极层上形成电介质（164），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些控制栅极和浮置栅极独立于光刻对准来定义。 在另一方面，非易失性存储单元具有至少两个导电浮动栅极（160）。 覆盖浮动栅极的介电层（164）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的侧壁的连续特征。 每个控制栅极（160）覆盖在电介质层的连续特征上并且也覆盖在浮动栅极上。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US20050095849A1

公开(公告)日：2005-05-05

申请号：US11013593

申请日：2004-12-14

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/48 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11529

Abstract: A widened contact area (170X) of a conductive feature (170) is formed by means of self-alignment between an edge (170E2) of the conductive feature and an edge (140E) of another feature (140). The other feature (“first feature”) is formed from a first layer, and the conductive feature is formed from a second layer overlying the first layer. The edge (170E2) of the conductive feature is shaped to provide a widened contact area. This shaping is achieved in a self-aligned manner by shaping the corresponding edge (140E) of the first feature.

Abstract translation: 通过在导电特征的边缘（170E2）与另一特征（140）的边缘（140E）之间的自对准，形成导电特征（170）的加宽的接触区域（170×）。 另一特征（“第一特征”）由第一层形成，并且导电特征由覆盖第一层的第二层形成。 导电特征的边缘（170E 2）成形为提供加宽的接触面积。 通过使第一特征的对应边缘（140E）成形，以自对准的方式实现该成形。

公开(公告)号：US20050023591A1

公开(公告)日：2005-02-03

申请号：US10632186

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/332 ,  H01L21/336 ,  H01L29/76

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/7887

Abstract: In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract translation: 在具有至少两个浮动栅极的非易失性存储单元中，每个浮动栅极（160）具有向上突出部分。 该部分可以形成为在选择门（140）的侧壁上的间隔物。 隔离物可以由沉积在提供浮动栅极的下部的层（160.1）之后的层（160.2）形成。 或者，向上突出部分和下部分可以由相同的层或子层形成，所有这些层或子层都存在于两个部分中。 控制栅极（170）可以在没有光刻的情况下被定义。 还提供了其他实施例。

公开(公告)号：US06744237B2

公开(公告)日：2004-06-01

申请号：US10063195

申请日：2002-03-28

Applicant: Bruce M. Kopf ,  Jing Song ,  Yi Ding

Inventor： Bruce M. Kopf ,  Jing Song ,  Yi Ding

IPC: H02J700

CPC classification number: B60L11/1887 ,  H01M10/44 ,  H01M16/003 ,  H01M2250/20 ,  H02J7/34 ,  H02J2001/004 ,  Y02T90/32 ,  Y02T90/34

Abstract: A hybrid power system (10) for supplying power to a load (12) such as an electric vehicle is provided. The power system (10) includes an energy storage device (14) and a fuel cell system (16). When the state of charge of the energy storage device (14) is greater than or equal to a predetermined state of charge, the energy storage device (14) supplies all of the power to the load (12). When the state of charge of the energy storage device (14) falls below the predetermined state of charge, the fuel cell system (16) supplies at least a portion of the power to the load (12). In accordance with one aspect of the invention, the fuel cell system (16) then supplies all of the power to the load (12) as long as the power requirement of the load (12) does not exceed an optimal power output of the fuel cell system (16).

Abstract translation: 提供了一种用于向诸如电动车辆的负载（12）供电的混合动力系统（10）。 电力系统（10）包括能量存储装置（14）和燃料电池系统（16）。 当能量存储装置（14）的充电状态大于或等于预定的充电状态时，能量存储装置（14）将所有的电力供应到负载（12）。 当能量存储装置（14）的充电状态低于预定的充电状态时，燃料电池系统（16）将至少一部分电力提供给负载（12）。 根据本发明的一个方面，燃料电池系统（16）然后只要负载（12）的功率需求不超过燃料的最佳功率输出即可将所有功率提供给负载（12） 细胞系统（16）。

公开(公告)号：US06434289B1

公开(公告)日：2002-08-13

申请号：US09676294

申请日：2000-09-28

Applicant: Mario J. Paniccia ,  Yi Ding ,  Dmitri E. Nikonov

Inventor： Mario J. Paniccia ,  Yi Ding ,  Dmitri E. Nikonov

IPC: G02B626

CPC classification number: G02F1/025 ,  G02B2006/12145

Abstract: A device for confining an optical beam in an optical switch. In one embodiment, the disclosed optical switch includes an optical switching device disposed between an optical input port and an optical output port in a semiconductor substrate layer disposed between a plurality of optical confinement layers such that an optical beam is confined to remain within the layers. In one embodiment, a plurality of semiconductor substrate layers are included in the optical switch. Each of the semiconductor substrate layers is disposed between optical confinement layers such that optical beams passing through the semiconductor substrate layers are confined to remain within the semiconductor substrate layers until exiting through respective optical output ports. In one embodiment, integrated circuitry such as driver circuitry, controller circuitry, logic circuitry, coder-decoder circuitry, microprocessor circuitry or the like is included in at least one of the semiconductor substrate layers.

Abstract translation: 用于将光束限制在光开关中的装置。 在一个实施例中，所公开的光开关包括设置在设置在多个光限制层之间的半导体衬底层中的光输入端口和光输出端口之间的光开关器件，使得光束被限制在残留在层内。 在一个实施例中，光开关中包括多个半导体衬底层。 每个半导体衬底层设置在光学限制层之间，使得通过半导体衬底层的光束被限制为保留在半导体衬底层内，直到通过相应的光学输出端口离开。 在一个实施例中，诸如驱动器电路，控制器电路，逻辑电路，编码器 - 解码器电路，微处理器电路等的集成电路被包括在至少一个半导体衬底层中。

公开(公告)号：US06374003B1

公开(公告)日：2002-04-16

申请号：US09410195

申请日：1999-09-30

Applicant: Yi Ding ,  Mario J. Paniccia

Inventor： Yi Ding ,  Mario J. Paniccia

IPC: G02B612

CPC classification number: G02F1/218 ,  G02B2006/12107 ,  G02B2006/12142 ,  G02F2001/0152 ,  G02F2201/307

Abstract: An optical modulator that modulates light through the semiconductor substrate through the back side of a flip chip packaged integrated circuit. In one embodiment, an optical modulator is disposed within a flip chip packaged integrated circuit die. The optical modulator includes a deflector and a diffraction grating. A first infrared optical beam having a photon energy less than the band gap energy of the semiconductor substrate is directed through the back side of the semiconductor substrate of the integrated circuit die, deflected off the deflector through the diffraction grating and back out the back side of the integrated circuit die. A second infrared optical beam having a photon energy greater than or equal to the band gap energy of the semiconductor substrate is directed through the back side of the semiconductor substrate to generate free charge carriers and increase the modulation depth of the optical modulator. The diffraction grating modulates the phase of a portion of the deflected optical beam in response to an integrated circuit signal. A resulting diffraction interference occurs between the phase modulated portions and non-phase modulated portions of the deflected optical beam. The interference causes amplitude modulation of the zeroth order diffraction or higher order diffractions of the deflected first optical beam, from which the integrated circuit signal can be extracted.

Abstract translation: 一种光学调制器，其通过倒装芯片封装集成电路的背面来调制通过半导体衬底的光。 在一个实施例中，光学调制器设置在倒装芯片封装集成电路管芯内。 光学调制器包括偏转器和衍射光栅。 具有小于半导体衬底的带隙能量的光子能量的第一红外光束被引导通过集成电路裸片的半导体衬底的背面，通过衍射光栅偏转偏转器并从背面侧退出 集成电路管芯。 具有大于或等于半导体衬底的带隙能量的光子能量的第二红外光束被引导通过半导体衬底的背面以产生自由电荷载流子并增加光调制器的调制深度。 衍射光栅响应于集成电路信号调制偏转光束的一部分的相位。 在偏转的光束的相位调制部分和非相位调制部分之间产生衍射干涉。 干涉引起偏转的第一光束的零级衍射的振幅调制或高阶衍射，从中可以提取集成电路信号。

公开(公告)号：US20190286686A1

公开(公告)日：2019-09-19

申请号：US16313146

申请日：2018-03-17

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G06F17/18 ,  G06F17/50 ,  G06F17/17

Abstract: An approximate evaluation method for reliability of a large-scale multi-state series-parallel system is provided, wherein for a multi-state series-parallel system, a connection structure between a parent node and all child nodes thereof is divided into four categories which are treated differently; according to the four categories, the probability distribution of the parent node of each level of a complete tree structure is calculated in turn from end leaf nodes; finally, probability distribution of a root parent node of the whole multi-state series-parallel system is obtained, thereby obtaining the reliability of the multi-state series-parallel system. The present invention realizes approximate evaluation of the reliability of the large-scale multi-state series-parallel system, and realizes a balance between calculation accuracy and calculation efficiency, so as to improve computational complexity from exponential complexity of originally accurate calculation to a quadratic term, thereby greatly improving a calculation speed.

公开(公告)号：US08854003B2

公开(公告)日：2014-10-07

申请号：US13476640

申请日：2012-05-21

Applicant: Yi Ding ,  Sonya G. Zanardelli ,  John M. Zwally

Inventor： Yi Ding ,  Sonya G. Zanardelli ,  John M. Zwally

IPC: H02J7/00

CPC classification number: G01R31/3634

Abstract: A method of rapidly testing the discharge capacity of a battery comprises discharging the battery at a first discharge rate until a first cutoff potential is reached, relaxing the battery during a first period, discharging the battery at a lower discharge rate until a second cutoff potential is reached and relaxing the battery during a second, longer period. The process is repeated with successively lower discharge rates and successively longer relaxation periods until the battery is substantially exhausted. The cumulative value of all of the discharges is taken as a tested capacity of the battery. Optionally, cleanup charges can be sent to the battery during the relaxation periods and a low-frequency, low-amplitude current can be supplied throughout testing in order to shorten testing time.

Abstract translation: 一种快速测试电池的放电容量的方法包括：以第一放电速率排出电池直到达到第一截止电位，在第一时段期间放电电池，以较低的放电速率放电电池，直至第二截止电位为 在更长时间内达到并放松电池。 该过程以连续较低的放电速率和连续较长的弛豫周期重复，直到电池充分耗尽。 将所有放电的累积值作为电池的测试容量。 可选地，在弛豫期间可以将清除电荷发送到电池，并且可以在整个测试期间提供低频，低振幅的电流，以缩短测试时间。

公开(公告)号：US08527577B2

公开(公告)日：2013-09-03

申请号：US11867635

申请日：2007-10-04

Applicant: Chengdong Lu ,  Wei Chen ,  Mi Zhou ,  Yi Ding

Inventor： Chengdong Lu ,  Wei Chen ,  Mi Zhou ,  Yi Ding

IPC: G06F15/16 ,  G06F17/20

CPC classification number: H04L29/06047 ,  H04L67/02 ,  H04L67/16 ,  H04L67/28 ,  H04L67/2823

Abstract: A computer enabled method and system that can expose distributed transaction services as web services from a service architecture comprises steps of configuring the service architecture; receiving a invocation request through web services from a client; invoking a distributed transaction service from a distributed transaction application, wherein the distributed transaction service is defined in the invocation request; and exporting the distributed transaction service in the form of web services.

Abstract translation: 一种能够从分布式事务服务作为Web服务从服务架构暴露的计算机启用的方法和系统包括配置服务体系结构的步骤; 通过客户端的Web服务接收调用请求; 从分布式事务应用程序调用分布式事务服务，其中在调用请求中定义分布式事务服务; 并以Web服务的形式导出分布式交易服务。