公开(公告)号：US20120044226A1

公开(公告)日：2012-02-23

申请号：US12895629

申请日：2010-09-30

Applicant: Surinder Pal Singh ,  Kaushik Saha ,  Sumit Johar

Inventor： Surinder Pal Singh ,  Kaushik Saha ,  Sumit Johar

IPC: G09G5/00

CPC classification number: G09G5/00 ,  G06T1/00

Abstract: An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic.

Abstract translation: 图像处理装置包括用于接收与图像处理装置相关的功率特性的指示符的输入和基于功率特性的指标来处理图像的图像处理器。

公开(公告)号：US20110299355A1

公开(公告)日：2011-12-08

申请号：US12840660

申请日：2010-07-21

Applicant: Vikas Rana

Inventor： Vikas Rana

IPC: G11C8/08

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。

公开(公告)号：US20110267125A1

公开(公告)日：2011-11-03

申请号：US12827225

申请日：2010-06-30

Applicant: Abhishek JAIN

Inventor： Abhishek JAIN

IPC: H03K3/289

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) master slave flip-flop with a single clock signal includes a master storage element configured to store an input data in response to a clock signal transition and a slave storage element configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition. The master storage element includes low threshold voltage transistors, the slave storage element includes high threshold voltage transistors, and the master and the slave storage elements are provided with a single clock signal.

Abstract translation: 具有单个时钟信号的多阈值互补金属氧化物半导体技术（MTCMOS技术）主从触发器包括被配置为响应于时钟信号转变来存储输入数据的主存储元件和被配置为接收的从存储元件 来自主存储元件的数据并且响应于相反的时钟信号转换来输出接收的数据。 主存储元件包括低阈值电压晶体管，从存储元件包括高阈值电压晶体管，并且主存储元件和从存储元件具有单个时钟信号。

公开(公告)号：US20110264971A1

公开(公告)日：2011-10-27

申请号：US12821038

申请日：2010-06-22

Applicant: Swapnil Bahl ,  Akhil Garg

Inventor： Swapnil Bahl ,  Akhil Garg

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/3177 ,  G01R31/318594

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Abstract translation: 用于在集成电路（IC）中测试多时钟域的系统包括耦合到多个时钟控制器的多个时钟源。 每个时钟源产生与多时钟域之一相关联的快速时钟。 每个时钟控制器配置为提供捕获脉冲以测试一个时钟域。 提供给时钟域的捕获脉冲处于与时钟域相关联的快速时钟的频率。 时钟控制器依次操作以提供捕获脉冲来测试时钟域。

公开(公告)号：US08041883B2

公开(公告)日：2011-10-18

申请号：US11801687

申请日：2007-05-09

Applicant: Sudeep Biswas ,  Angelo Di Sena ,  Domenico Manna

Inventor： Sudeep Biswas ,  Angelo Di Sena ,  Domenico Manna

IPC: G06F12/10

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7209 ,  G06F2212/7211

Abstract: A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.

Abstract translation: 提出了一种基于闪速存储器来恢复存储设备的操作的解决方案。 存储装置模拟映射到闪速存储器的物理存储器空间的逻辑存储器空间（包括具有多个逻辑扇区的多个逻辑块），每个逻辑块包括多个物理块，每个具有多个 用于存储逻辑扇区的不同版本的物理扇区）。 相应的方法通过检测用于损坏的逻辑块（由存储设备的故障导致）的多个冲突的物理块开始。 该方法通过确定多个有效性索引（指示存储在冲突的物理块中的损坏的逻辑块的逻辑扇区的最后版本的数量）来继续。 根据有效性指标选择一个以上的冲突物理块。 所选冲突的物理块然后与损坏的逻辑块相关联。 最后，每个未选择的冲突物理块被丢弃。

公开(公告)号：US08035451B2

公开(公告)日：2011-10-11

申请号：US12636663

申请日：2009-12-11

Applicant: Anand Kumar

Inventor： Anand Kumar

IPC: H03L7/06 ,  H03L7/18

CPC classification number: H03L7/1972

Abstract: A difference between a reference clock and feedback clock is detected to generate a difference signal that is filtered to generate a voltage controlled oscillator control signal and produce an oscillation signal having an oscillation frequency. A first frequency dividing circuit divides the oscillation signal by a selected one of a number of first frequency divisors to generate an output signal at a selected frequency. A second frequency dividing circuit divides the output signal by a selected one of a number of second frequency divisors to generate the feedback clock. The frequency divisors are selected by a frequency selection signal. The first frequency dividing circuit samples the frequency selection signal at the rate of the oscillation signal divided by a least common multiple of the plurality of first frequency divisors. The second frequency dividing circuit samples the sampled frequency selection signal at the rate of the feedback clock.

Abstract translation: 检测参考时钟和反馈时钟之间的差异，以产生被滤波的差分信号，以产生压控振荡器控制信号并产生具有振荡频率的振荡信号。 第一分频电路将振荡信号除以多个第一频率除数中的所选择的一个，以产生所选频率的输出信号。 第二分频电路将输出信号除以多个第二频率因数中的一个，以产生反馈时钟。 频率除数由频率选择信号选择。 第一分频电路按照振荡信号的频率除以多个第一频率除数的最小公倍数来对频率选择信号进行采样。 第二分频电路按照反馈时钟的速率对采样的频率选择信号进行采样。

公开(公告)号：US20110153934A1

公开(公告)日：2011-06-23

申请号：US12974179

申请日：2010-12-21

Applicant: Alok Kumar MITTAL ,  Deepak Naik

Inventor： Alok Kumar MITTAL ,  Deepak Naik

IPC: G06F12/00

CPC classification number: G06K19/07732 ,  G06F3/0661 ,  G06F5/06 ,  G06F2213/3804 ,  G06F2213/3852

Abstract: A memory card and a communication method between a memory card and a host unit are disclosed. High throughput of data between the memory card and the host unit is guaranteed by providing a communication interface between the memory card and the host unit including a first communication interface between a memory unit of the memory card and a control unit of the memory card and a second communication interface between the control unit of the memory card and the host unit.

Abstract translation: 公开了一种存储卡和存储卡与主机之间的通信方法。 通过提供存储卡和主机单元之间的通信接口来保证存储卡和主机单元之间的高吞吐量，包括存储卡的存储器单元和存储卡的控制单元之间的第一通信接口和 存储卡的控制单元与主机单元之间的第二通信接口。

公开(公告)号：US20110150351A1

公开(公告)日：2011-06-23

申请号：US12702497

申请日：2010-02-09

Applicant: Surinder Pal SINGH ,  Aneesh Bhasin ,  Kaushik Saha

Inventor： Surinder Pal SINGH ,  Aneesh Bhasin ,  Kaushik Saha

IPC: G06K9/36 ,  H03M7/40

CPC classification number: G06T9/005 ,  H03M7/40 ,  H04N19/436 ,  H04N19/44 ,  H04N19/46 ,  H04N19/91

Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

Abstract translation: 用可变长度码编码的数据流的解码的并行化包括确定一个或多个标记，每个标记表示编码数据流内的位置。 确定的标记与编码数据一起被包括在编码数据流中。 在解码器侧，从编码数据流中解析出标记，并根据提取的标记进行解析。 编码数据被分成分开并且并行解码的分区。

公开(公告)号：US20110115561A1

公开(公告)日：2011-05-19

申请号：US12622167

申请日：2009-11-19

Applicant: Surendra Kumar ,  Tapas Nandy

Inventor： Surendra Kumar ,  Tapas Nandy

IPC: H03F3/45

CPC classification number: H03F3/45071 ,  H03F1/0266 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45302 ,  H03F2203/45354 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45446 ,  H03F2203/45702

Abstract: A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage.

Abstract translation: 电路包括具有折叠共源共栅结构的差分放大器和一对共源共栅晶体管。 感测电路感测施加到差分放大器的差分输入信号的共模输入电压。 偏置发生器电路在折叠共源共栅结构中产生用于施加到该对共源共栅晶体管的偏置电压。 偏置发生器电路连接到感测电路的输出，使得产生的偏置电压具有取决于感测到的共模输入电压的值。 这种依赖性响应于共模输入电压的变化而稳定来自差分放大器的共模输出电压。

公开(公告)号：US07944245B2

公开(公告)日：2011-05-17

申请号：US12339024

申请日：2008-12-18

Applicant: Saurabh Saxena

Inventor： Saurabh Saxena

IPC: H03K5/00

CPC classification number: H03K5/1252

Abstract: A filtering module filters out high frequency signals, primarily noise, from an input data stream. The filtering module includes an input module, a phase detecting module, and a threshold module. The input module performs either a charging or a discharging across a capacitor on a basis of an RC time constant. The phase detecting module is coupled to the input module to keep identical phase at a first node and an output node. The threshold module is coupled to the phase detecting module for providing an output signal based on a threshold voltage and the charging or the discharging across the capacitor.

Abstract translation: 滤波模块从输入数据流滤除高频信号，主要是噪声。 滤波模块包括输入模块，相位检测模块和阈值模块。 输入模块在RC时间常数的基础上，对电容器进行充电或放电。 相位检测模块耦合到输入模块以在第一节点和输出节点处保持相同的相位。 阈值模块耦合到相位检测模块，用于基于阈值电压和电容器两端的充电或放电来提供输出信号。