公开(公告)号：US20110234528A1

公开(公告)日：2011-09-29

申请号：US12732581

申请日：2010-03-26

Applicant: Yannick Guedon ,  Kien Beng Tan

Inventor： Yannick Guedon ,  Kien Beng Tan

IPC: G06F3/045 ,  H03M1/12

CPC classification number: H03M11/20 ,  G06F3/0416 ,  G06F3/044 ,  H03K2217/960725 ,  H03M3/43

Abstract: A circuit for converting charge measured from a touch screen into a digital signal can include a sample and hold circuit. The sample and hold circuit can sample and integrate a charge from a capacitive sense matrix, and hold a voltage signal representing the measured charge. A sigma delta converter can convert the voltage into a digital value.

Abstract translation: 用于将从触摸屏测量的电荷转换为数字信号的电路可以包括采样和保持电路。 采样和保持电路可以对来自电容检测矩阵的电荷进行采样和积分，并保持表示测量电荷的电压信号。 Σ-Δ转换器可将电压转换为数字值。

公开(公告)号：US08018036B2

公开(公告)日：2011-09-13

申请号：US11602098

申请日：2006-11-20

Applicant: Kim-yong Goh ,  Tong-yan Tee

Inventor： Kim-yong Goh ,  Tong-yan Tee

IPC: H01L23/24

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract translation: 一种超薄四边形扁平无铅（QFN）半导体芯片封装，其具有引线框架，该引线框架具有由顶部和底部表面的凹部形成的引线端子和形成在顶部或底部表面上的基本上对准的接触区域。 模具电连接到多个引线端子，并且模制化合物将引线框封装在一起，以形成超薄QFN封装。 因此，基本对准的接触区域暴露在封装的顶表面和底表面上。 本公开还提供了一种超薄光学四方扁平无引线（OQFN）半导体芯片封装，包括至少两个QFN半导体芯片封装的堆叠半导体模块，以及用于制造超薄四面体扁平无铅 QFN）半导体封装。

公开(公告)号：US08013438B2

公开(公告)日：2011-09-06

申请号：US12507049

申请日：2009-07-21

Applicant: Jing-En Luan ,  Kum-Weng Loo

Inventor： Jing-En Luan ,  Kum-Weng Loo

IPC: H01L23/34

CPC classification number: H01L23/16 ,  H01L23/3121 ,  H01L23/36 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/16152 ,  H01L2924/19105

Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.

Abstract translation: 半导体封装包括衬底板和附接到该衬底板的顶表面的半导体管芯。 散热器设置在半导体管芯上。 加强环定位在半导体模具周围，加强环附接到基板的顶表面并且附接到散热器的板部分的底表面。 空间留在加强环外部的板上，以支持将无源部件安装到基板上。 可以包括外部环，该外环通过一组连接杆与加强环相互连接。 或者，散热器包括整体形成的外围侧壁部分。

公开(公告)号：US08004340B2

公开(公告)日：2011-08-23

申请号：US12633597

申请日：2009-12-08

Applicant: Dianbo Guo ,  Eng Jye Ng ,  Kien Beng Tan

Inventor： Dianbo Guo ,  Eng Jye Ng ,  Kien Beng Tan

IPC: H03L5/00

CPC classification number: H03K17/164

Abstract: In one embodiment, a semiconductor circuit for coupling a first node to a second node includes a first transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a control node. The circuit also includes a level shifting circuit having a series diode for coupling a bulk terminal of the first transistor to the control node, and a supply coupling circuit coupled between a first power supply node and the control node.

Abstract translation: 在一个实施例中，用于将第一节点耦合到第二节点的半导体电路包括具有耦合到第一节点的第一终端的第一晶体管，耦合到第二节点的第二终端以及耦合到控制节点的控制终端。 电路还包括具有用于将第一晶体管的体端子耦合到控制节点的串联二极管的电平移动电路和耦合在第一电源节点和控制节点之间的电源耦合电路。

公开(公告)号：US20110157436A1

公开(公告)日：2011-06-30

申请号：US12649746

申请日：2009-12-30

Applicant: Patricia Chiang Wei Yin

Inventor： Patricia Chiang Wei Yin

IPC: H04N5/208 ,  G06K9/40

CPC classification number: H04N5/208

Abstract: A system is disclosed for reducing artifacts in images and video, such as ringing or halo artifacts. The system may include an edge detector and a gain controller. The edge detector may create an edge image used by the gain controller to create a gain image, and the gain image may be used to reduce artifacts in an image. The gain controller may, for a current pixel in the edge image, compute the maximum value of the edge image over a window containing the current pixel. The gain controller may also perform averaging to determine a maximum edge value and a current edge value, and may also use a ratio of the current edge value and the maximum edge value to determine a gain to be applied to a pixel of an image.

Abstract translation: 公开了一种用于减少图像和视频中的伪影的系统，例如振铃或光晕伪影。 系统可以包括边缘检测器和增益控制器。 边缘检测器可以创建由增益控制器使用的边缘图像以产生增益图像，并且增益图像可以用于减少图像中的伪像。 对于边缘图像中的当前像素，增益控制器可以在包含当前像素的窗口上计算边缘图像的最大值。 增益控制器还可以执行平均以确定最大边缘值和当前边缘值，并且还可以使用当前边缘值和最大边缘值的比率来确定要施加到图像的像素的增益。

公开(公告)号：US07961888B2

公开(公告)日：2011-06-14

申请号：US11280952

申请日：2005-11-16

Applicant: Sudhir K. Kasargod ,  Sapna George

Inventor： Sudhir K. Kasargod ,  Sapna George

IPC: H04R5/00 ,  H03G5/00 ,  H04B1/00

CPC classification number: H04S1/002 ,  H03G5/04

Abstract: The quality of music output from audio systems is improved by simulating the effect of low frequency signals in the human ear. This thus allows listeners to perceive the lower frequency signals, even though the speakers may be incapable of providing such low frequency outputs. A method is provided for processing enhancing bass effect in audio signals. The method also results in the bass enhancement being computationally less intensive. The bass effect enhancement techniques are based on the response of sine and cosine transfer functions and on the directional independence of low frequency components. The human ear is unable to resolve directions from low frequency components. The bass effect enhancement technique alternatively is based on response of an exponential transfer function.

Abstract translation: 通过模拟人耳中低频信号的影响，改善了音频系统音乐输出的质量。 因此，即使扬声器不能提供这样的低频输出，因此允许听众感知较低频率信号。 提供一种用于处理音频信号中增强低音效果的方法。 该方法还导致低音增强在计算上不太密集。 低音效果增强技术基于正弦和余弦传递函数的响应以及低频分量的方向独立性。 人耳不能解决低频部件的方向。 低音效果增强技术或者基于指数传递函数的响应。

公开(公告)号：US20110129024A1

公开(公告)日：2011-06-02

申请号：US12963569

申请日：2010-12-08

Applicant: Muralidhar KARTHIK ,  George A. VLANTIS

Inventor： Muralidhar KARTHIK ,  George A. VLANTIS

IPC: H04L27/00 ,  H04K1/10

CPC classification number: H04L25/022 ,  H04L25/0204 ,  H04L25/0224 ,  H04L25/03821 ,  H04L27/2601

Abstract: In an embodiment, a channel estimator includes first and second stages. The first stage is operable to generate a respective one-dimensional array of first channel-estimation coefficients for each communication path of a communication channel, and the second stage is operable to generate a multi-dimensional array of second channel-estimation coefficients in response to the first channel-estimation coefficients. For example, such a channel estimator may estimate the response of a channel over which propagates an orthogonal-frequency-division-multiplexed (OFDM) signal that suffers from inter-carrier interference (ICI) due to Doppler spread. Such a channel estimator may estimate the channel response more efficiently, and with a simpler algorithm, than conventional channel estimators. Furthermore, such a channel estimator may be able to dynamically account for changes in the number of communication paths that compose the channel, for changes in the delays of these paths, or the portions of the transmitted symbol energy carried by these paths.

Abstract translation: 在一个实施例中，信道估计器包括第一和第二阶段。 第一级可操作以产生用于通信信道的每个通信路径的第一信道估计系数的相应一维阵列，并且第二级可操作以响应于第二信道估计系数生成第二信道估计系数的多维阵列 第一个信道估计系数。 例如，这样的信道估计器可以估计传播由于多普勒扩展而遭受载波间干扰（ICI）的正交频分复用（OFDM）信号的信道的响应。 这样的信道估计器可以比传统的信道估计器更有效地估计信道响应，并且使用更简单的算法来估计信道响应。 此外，这样的信道估计器可能能够动态地考虑构成信道的通信路径的数量的变化，这些路径的延迟的改变或由这些路径携带的所发送的符号能量的部分的变化。

公开(公告)号：US07948114B2

公开(公告)日：2011-05-24

申请号：US12324273

申请日：2008-11-26

Applicant: Chee Yu Ng

Inventor： Chee Yu Ng

IPC: H02J3/14

CPC classification number: H02J1/14 ,  Y10T307/414

Abstract: An apparatus and method are disclosed for providing a power switch array with adjustable current rating power switches. A plurality of current rating power switches is provided that connects a power supply unit to a plurality of device ports. A power switch array controller is provided that adjusts an adjustable current rating in each of the plurality of adjustable current rating power switches. Each of the plurality of adjustable current rating power switches is adjustable to a selected number of current values. The power switch array controller dynamically adjusts the current ratings in the adjustable current power switches as required by the current requirements of the device ports.

Abstract translation: 公开了一种用于提供具有可调电流额定功率开关的功率开关阵列的装置和方法。 提供了将电源单元连接到多个设备端口的多个额定功率开关。 提供了一种功率开关阵列控制器，其调节多个可调电流额定功率开关中的每一个中的可调电流额定值。 多个可调电流额定功率开关中的每一个可调节到选定数量的电流值。 电源开关阵列控制器根据设备端口的当前要求动态调整可调电流电源开关中的电流额定值。

公开(公告)号：US20110089920A1

公开(公告)日：2011-04-21

申请号：US12580157

申请日：2009-10-15

Applicant: Kong Yin Leong ,  Soon Hwei Tan

Inventor： Kong Yin Leong ,  Soon Hwei Tan

IPC: G05F1/10

CPC classification number: H02M3/157 ,  H02M3/1582 ,  H02M3/1584

Abstract: A dual supply circuit uses a dual feedback control, single inductor, dual polarity boost architecture with a low side power FET for end of current recirculation sensing. A dual feedback system tracks the output voltage variations and a low side power FET end of current recirculation sensing utilizes the internal current limit sensing system. Logic defining the state of operations allows the regulator to operate in both single and dual mode to cater to wide application ranges. The positive boost regulator can be operated in a buck mode making the output voltage constant with high input supply.

Abstract translation: 双电源电路采用双反馈控制，单电感，双极性升压架构和低端功率FET，用于电流再循环检测。 双反馈系统跟踪输出电压变化，并且电流再循环感测的低端功率FET端利用内部限流检测系统。 定义操作状态的逻辑允许调节器以单模式和双模式运行，以适应广泛的应用范围。 正升压稳压器可以在降压模式下工作，使输出电压恒定，输入电源高。

公开(公告)号：US07860338B2

公开(公告)日：2010-12-28

申请号：US11623504

申请日：2007-01-16

Applicant: Fritz Lebowsky ,  Yong Huang ,  Haiyun Wang

Inventor： Fritz Lebowsky ,  Yong Huang ,  Haiyun Wang

IPC: G06K9/40 ,  G06K9/48

CPC classification number: G06T3/403

Abstract: A device processes an initial digital image with at least one contour zone. The device may have a magnifier able to magnify the initial image into a magnified digital image. The magnifier may have a detector able to detect the contour zones of the initial digital image, a determinater able to determine the size, in terms of number of pixels, of each contour zone, and a second magnifier able to magnify each contour zone using of a software tool, chosen as a function of the size of each contour zone, from among a set of magnifying software tools.

Abstract translation: 设备使用至少一个轮廓区域来处理初始数字图像。 该装置可以具有能够将初始图像放大成放大数字图像的放大镜。 放大镜可以具有能够检测初始数字图像的轮廓区域的检测器，能够根据每个轮廓区域的像素数确定尺寸的确定器，以及能够使用 从一组放大软件工具中选择作为每个轮廓区域的大小的函数的软件工具。