公开(公告)号：US09041372B2

公开(公告)日：2015-05-26

申请号：US13799492

申请日：2013-03-13

Applicant: Analog Devices Technology

Inventor： Renjian Xie ,  Qingyi Huang ,  Yingyang Ou

IPC: G05F1/00 ,  H02M3/158 ,  H02M1/00

CPC classification number: H02M3/1582 ,  H02M2001/007 ,  Y10T307/25

Abstract: A switching power converter includes a voltage source that provides an input voltage Vin to an unregulated DC/DC converter stage and at least one buck-boost converter stage to produce a desired output voltage Vout. The unregulated DC/DC converter stage is adapted to provide an isolated voltage to the at least one regulated buck-boost converter stage, wherein the unregulated DC/DC converter stage comprises a transformer having a primary winding and at least one secondary winding and at least one switching element coupled to the primary winding. The at least one buck-boost converter stage is arranged to operate in a buck mode, boost mode or buck-boost mode in response to a mode selection signal from a mode selection module. By influencing the pulse width modulation output power controller the at least one buck-boost converter stage is arranged to produce one or multiple output voltages.

Abstract translation: 开关功率转换器包括向未调节的DC / DC转换器级和至少一个降压 - 升压转换器级提供输入电压Vin以产生期望的输出电压Vout的电压源。 未调节的DC / DC转换器级适于向至少一个调节的降压 - 升压转换器级提供隔离电压，其中未调节的DC / DC转换器级包括具有初级绕组和至少一个次级绕组的变压器，并且至少 一个开关元件耦合到初级绕组。 至少一个降压 - 升压转换器级被布置成响应于来自模式选择模块的模式选择信号而以降压模式，升压模式或降压 - 升压模式操作。 通过影响脉宽调制输出功​​率控制器，至少一个降压 - 升压转换器级布置成产生一个或多个输出电压。

公开(公告)号：US20150139283A1

公开(公告)日：2015-05-21

申请号：US14085443

申请日：2013-11-20

Applicant: Analog Devices Technology

Inventor： Michael Dalton

IPC: H04L7/00 ,  H04L7/06 ,  H04L27/00

CPC classification number: H04L7/0087 ,  H04B1/38 ,  H04L7/042 ,  H04L7/06 ,  H04L27/0014 ,  H04L2027/0036 ,  H04L2027/0095

Abstract: A method for detecting a preamble in a received radio signal comprises demodulating a received radio signal based on a carrier derived from a local timing source to provide a digital signal comprising a sequence of bits oscillating at approximately a modulated data rate. A bit width of each successive bit of the digital signal is determined. If a pair of consecutive bit widths have a combined width within a threshold value, the bit pair is indicated as potentially belonging to a preamble. If a threshold number of potential preamble bit pairs in a sequence of bit pairs within a given window is detected, the sequence of bit pairs is indicated as potentially comprising a preamble. A measure of bit widths of at least some bits within a sequence of preamble bit pairs can be provided and a frequency of the local timing source can be adjusted according to said measure.

Abstract translation: 用于检测接收到的无线电信号中的前同步码的方法包括基于从本地定时源导出的载波来解调所接收的无线电信号，以提供包括以大约调制数据速率振荡的比特序列的数字信号。 确定数字信号的每个连续位的位宽度。 如果一对连续比特宽度具有在阈值内的组合宽度，则该比特对被指示为潜在地属于前导码。 如果检测给定窗口内的位对序列中的潜在前导码比特对的阈值数目，则将该比特对的序列指示为潜在地包括前导码。 可以提供在前导码比特对序列内的至少一些比特的比特宽度的度量，并且可以根据所述测量来调整本地定时源的频率。

公开(公告)号：US20150136853A1

公开(公告)日：2015-05-21

申请号：US14086793

申请日：2013-11-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Joseph Wayne Palmer ,  Paul Vincent Errico ,  Liam Patrick Riordan ,  Juan Francisco Escobar Valero

IPC: G06K7/08 ,  G06K19/067

CPC classification number: G06K7/081 ,  G06K19/067

Abstract: A low-cost system comprising a pattern arranged to encode information and a decoder for decoding the information encoded in the pattern is described. In particular, the mechanism employs a capacitive sensing technique. Electrodes are arranged (or stimulated, during operation) to each generate an electric field, and sense disturbances on the electric field caused by the pattern when the pattern is positioned over the electrodes. The spatial arrangement of the pattern allows information to be encoded on a strip or surface and decoded by capacitive sensors arranged to detect disturbances caused by possible patterns. The resulting solution is cheaper and less complex than optical solutions, e.g., barcodes and optical barcode readers. The mechanism may be used in a glucose meter for encoding and decoding an identifier for distinguishing batches of glucose meter test strips.

Abstract translation: 描述了一种低成本系统，其包括布置成编码信息的模式和用于解码在模式中编码的信息的解码器。 特别地，该机构采用电容感测技术。 电极被布置（或在操作期间被刺激）以产生电场，并且当图案位于电极上方时，感测由图案引起的电场上的扰动。 模式的空间排列允许将信息编码在条带或表面上，并通过布置成检测由可能图案引起的干扰的电容传感器进行解码。 所得到的解决方案比诸如条形码和光学条形码读取器的光学解决方案更便宜并且更不复杂。 该机制可以用于葡萄糖计中，用于编码和解码用于区分葡萄糖计测试条的批次的标识符。

公开(公告)号：US20150131848A1

公开(公告)日：2015-05-14

申请号：US14076030

申请日：2013-11-08

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Prasanna Baja Thirumaleshwara ,  Vijaykumar Nagarajan

IPC: G06K9/00 ,  G06K9/62 ,  G06T11/60 ,  G06K9/46

CPC classification number: G06K9/00624 ,  G06K9/4604 ,  G06K9/4642 ,  G06K9/6267 ,  G06K9/6269 ,  G06N99/005 ,  G06T11/60

Abstract: An exemplary object detection method includes generating feature block components representing an image frame, and analyzing the image frame using the feature block components. For each feature block row of the image frame, feature block components associated with the feature block row are evaluated to determine a partial vector dot product for detector windows that overlap a portion of the image frame including the feature block row, such that each detector window has an associated group of partial vector dot products. The method can include determining a vector dot product associated with each detector window based on the associated group of partial vector dot products, and classifying an image frame portion corresponding with each detector window as an object or non-object based on the vector dot product. Each feature block component can be moved from external memory to internal memory once implementing the exemplary object detection method.

Abstract translation: 示例性对象检测方法包括生成表示图像帧的特征块分量，以及使用特征块分量来分析图像帧。 对于图像帧的每个特征块行，评估与特征块行相关联的特征块分量，以确定与包括特征块行的图像帧的一部分重叠的检测器窗口的部分矢量点积，使得每个检测器窗口 具有相关组的部分矢量点积。 该方法可以包括基于相关组的部分矢量点积来确定与每个检测器窗口相关联的矢量点积，并且基于矢量点积将对应于每个检测器窗口的图像帧部分分类为对象或非对象。 一旦实现了示例性对象检测方法，每个特征块组件可以从外部存储器移动到内部存储器。

公开(公告)号：US20150123256A1

公开(公告)日：2015-05-07

申请号：US14072572

申请日：2013-11-05

Applicant: Analog Devices Technology

Inventor： Oliver J Kierse ,  Frank Poucher ,  Michael J. Cusack ,  Padraig L. Fitzgerald ,  Patrick Elebert

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L23/16 ,  H01L23/295 ,  H01L23/31 ,  H01L23/3107 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die such that the shield plate covers less than all of the top surface and leaves bond pads exposed. A molding material is applied over the shield plate and the integrated circuit die. The shield plate shields the integrated circuit die from stresses imparted by the molding material.

Abstract translation: 公开了一种塑料集成电路封装的应力屏蔽。 屏蔽板通过粘合剂附接到集成电路管芯的顶表面，使得屏蔽板覆盖小于所有顶表面并且留下暴露的接合焊盘。 将模制材料施加在屏蔽板和集成电路模具上。 屏蔽板屏蔽集成电路模具与模制材料施加的应力。

公开(公告)号：US20150109158A1

公开(公告)日：2015-04-23

申请号：US14057153

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yunzhi Dong ,  Hajime Shibata ,  Wenhua W. Yang ,  Richard E. Schreier

IPC: H03M3/00

CPC classification number: H03M3/344 ,  H03M1/00 ,  H03M1/12 ,  H03M1/144 ,  H03M1/145 ,  H03M3/30 ,  H03M3/416 ,  H04L25/067 ,  H04M1/72519

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (ΔΣ) modulator is provided at the front-end of the MASH ADC, and another full ΔΣ modulator is provided at the back-end of the MASH ADC. The front-end ΔΣ modulator digitizes an analog input signal, and the back-end ΔΣ modulator digitizes an error between the output of the front-end ΔΣ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract translation: 本公开描述了一种用于将模拟输入信号转换为数字输出信号的改进的多级噪声整形（MASH）模数转换器（ADC）。 特别地，在MASH ADC的前端提供了一个完整的delta-sigma（＆Dgr＆amp; Sgr）调制器，另一个完整的＆Dgr＆amp; 调制器设置在MASH ADC的后端。 前端＆Dgr＆＆ 调制器将模拟输入信号数字化，后端＆Dgr＆amp; 调制器数字化前端＆Dgr＆amp; Sgr的输出之间的误差; 调制器和（原始）模拟输入信号。 在这种配置中，后端调制器将（全）前端调制器的误差数字化，前端的一些设计约束被放宽。 这些设计约束包括热噪声，数字噪声消除滤波器复杂度（前端的量化噪声已经由前端的噪声传递函数形成）和/或非线性。

公开(公告)号：US20150036390A1

公开(公告)日：2015-02-05

申请号：US13955971

申请日：2013-07-31

Applicant: Analog Devices Technology

Inventor： Yingyang Ou ,  Renjian Xie ,  Qingyi Huang

IPC: H02M3/337

CPC classification number: H02M3/337 ,  H02M3/33592 ,  Y02B70/1475

Abstract: An apparatus comprises a power converter circuit and a control circuit. The power converter circuit includes a primary circuit side and a secondary circuit side. The primary circuit side includes a plurality of primary switches, and the secondary circuit side includes a plurality of synchronous rectifiers and an inductor. The control circuit is configured to operate the synchronous rectifiers synchronously with the primary switches when inductor current at the inductor is greater than or equal to a reference inductor current, and operate the synchronous rectifiers in a bidirectional mode when the inductor current is less than the reference inductor current, wherein energy is delivered from the primary side to the secondary side and from the secondary side to the primary side during the bidirectional mode.

Abstract translation: 一种装置包括功率转换器电路和控制电路。 功率转换器电路包括初级电路侧和次级电路侧。 主电路侧包括多个初级开关，次级电路侧包括多个同步整流器和电感器。 控制电路被配置为当电感器上的电感电流大于或等于参考电感器电流时与主开关同步地操作同步整流器，并且当电感器电流小于参考电压时，以双向模式操作同步整流器 电感电流，其中在双向模式期间，能量从初级侧传递到次级侧，从次级侧传递到初级侧。

公开(公告)号：US20150022386A1

公开(公告)日：2015-01-22

申请号：US13945647

申请日：2013-07-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Kevin Cao-Van Lam ,  Richard E. Schreier ,  Donald W. Paterson

IPC: H03M1/10

CPC classification number: H03M3/38 ,  H03M1/1009 ,  H03M3/392 ,  H03M3/424 ,  H03M3/454

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by denormalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value. In some embodiments, the integrated circuit further includes a scaling module configured to scale the component value based on scaling parameters.

Abstract translation: 集成电路包括：组件计算器，被配置为从至少一个应用参数计算高可编程模数转换器（ADC）的至少一个分量值;以及映射模块，被配置为将分量值映射到对应的寄存器设置 基于至少一个工艺参数，其中所述集成电路产生能够编程所述ADC的数字控制信号。 在具体实施例中，组件计算器使用应用参数的归一化表示的代数函数来近似评估至少一个归一化的ADC系数。 通过对归一化的ADC系数进行非归一化来进一步计算分量值。 在另一具体实施例中，组件计算器使用应用参数的代数函数来计算组件值。 在一些实施例中，集成电路还包括缩放模块，其被配置为基于缩放参数来缩放分量值。

公开(公告)号：US08928390B2

公开(公告)日：2015-01-06

申请号：US13848929

申请日：2013-03-22

Applicant: Analog Devices Technology

Inventor： Eberhard Brunner

IPC: G06G7/20 ,  G01R19/02

CPC classification number: G01R19/02

Abstract: A root-mean-square (RMS) detector includes detection circuitry having as an input a radio frequency signal, target voltage and a set voltage and a RMS signal as an output, and a gain stage within the detection circuitry to produce the RMS signal as an output. The gain stage provides for faster settling times of the detector.

Abstract translation: 均方根（RMS）检测器包括检测电路，其具有作为输入的射频信号，目标电压和设定电压以及RMS信号作为输出，以及检测电路内的增益级，以产生RMS信号作为 一个输出。 增益级提供检测器更快的建立时间。

公开(公告)号：US20140340422A1

公开(公告)日：2014-11-20

申请号：US13896105

申请日：2013-05-16

Applicant: Analog Devices Technology

Inventor： Himanshu Srivastava

IPC: G06T11/60

Abstract: An apparatus includes a processing unit that divides an overlay buffer into a plurality of macro blocks, draws a graphic primitive object including a plurality of pixels, identifies one of the plurality of macro blocks upon a determination that the plurality of pixels has crossed a boundary of the one of the plurality of macro blocks, and image processes the one of the plurality of macro blocks.

Abstract translation: 一种装置包括：处理单元，其将覆盖缓冲区划分成多个宏块，绘制包括多个像素的图形原始对象，在确定所述多个像素已经跨越所述多个像素的边界时识别所述多​​个宏块中的一个， 多个宏块中的一个，并且图像处理多个宏块中的一个。