公开(公告)号：US10555060B2

公开(公告)日：2020-02-04

申请号：US16419793

申请日：2019-05-22

Applicant: SOCIONEXT INC.

Inventor： Shuji Miyasaka ,  Kazutaka Abe ,  Katsumi Kobayashi

IPC: H04R1/02 ,  B62D1/04 ,  H04R5/02 ,  H04S7/00

Abstract: An acoustic device that provides a stereophonic effect to a driver of a mobile object includes: a plurality of speakers (an L channel speaker and an R channel speaker) mounted on a steering wheel that controls a traveling direction of the mobile object; a steering angle detection unit configured to detect a steering angle of the steering wheel; and a signal output unit configured to output a plurality of output signals obtained by performing, on a sound signal, a process relating to the stereophonic effect and depending on the steering angle, respectively to the plurality of speakers.

公开(公告)号：US10554214B2

公开(公告)日：2020-02-04

申请号：US16243994

申请日：2019-01-09

Applicant: SOCIONEXT INC.

Inventor： Niklas Linkewitsch ,  Charles Joseph Dedic

IPC: H03M1/06 ,  H03M1/10

Abstract: A non-linearity evaluation circuit for use with a signal generator having at least a partly non-linear operation. The non-linearity evaluation circuit may include a detection unit operable to detect a given amplitude attribute in a target signal generated by the signal generator, a time position of the amplitude attribute in the target signal defining a time location of a snapshot time window relative to the target signal, a part of the target signal occupying the snapshot time window being a corresponding signal snapshot, and a presence of the given amplitude attribute indicating that the signal snapshot includes noise due to the non-linear operation of the signal generator. The non-linearity evaluation circuit may further include a controller operable to analyse the signal snapshot rather than a larger part of the target signal and to evaluate the non-linear characteristics of the operation of the signal generator based on the analysis.

公开(公告)号：US20200007104A1

公开(公告)日：2020-01-02

申请号：US16410437

申请日：2019-05-13

Applicant: SOCIONEXT INC.

Inventor： Atheer Sami BARGHOUTHI ,  Saul DARZY

IPC: H03H7/00 ,  H02H9/04

Abstract: An interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node; a signal pair of inductors connected in series along the signal line adjacent to and either side signal node; and an auxiliary pair of inductors connected in series along the signal line adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; and kS has a positive value and kA has a negative value.

公开(公告)号：US20200006321A1

公开(公告)日：2020-01-02

申请号：US16565380

申请日：2019-09-09

Applicant: SOCIONEXT INC.

Inventor： Shiro USAMI

IPC: H01L27/02 ,  H01L29/861 ,  H01L23/528 ,  H01L29/87

Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

公开(公告)号：US20190393206A1

公开(公告)日：2019-12-26

申请号：US16438026

申请日：2019-06-11

Applicant: SOCIONEXT INC.

Inventor： Wenzhen WANG ,  Hirotaka TAKENO ,  Atsushi OKAMOTO

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

公开(公告)号：US10446492B2

公开(公告)日：2019-10-15

申请号：US15982766

申请日：2018-05-17

Applicant: SOCIONEXT INC.

Inventor： Tooru Matsui ,  Masahiro Yoshimura

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/60 ,  H02H9/04 ,  H01L27/02

Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.

公开(公告)号：US10432182B2

公开(公告)日：2019-10-01

申请号：US16194649

申请日：2018-11-19

Applicant: SOCIONEXT INC.

Inventor： Jun Nagayama

IPC: H03K5/135 ,  H03K5/14 ,  H01L27/04 ,  H03K5/00 ,  G06F1/3237

Abstract: In a monitor circuit, a data signal is propagated from an FF to another FF via a data delay circuit. The data delay circuit selects any one from among data paths that delay the data signal in accordance with a selection signal. A clock signal that is input to the FF is input to the other FF via a clock delay circuit. The clock delay circuit selects any one from among clock paths that delay the clock signal in accordance with another selection signal.

公开(公告)号：US10382679B2

公开(公告)日：2019-08-13

申请号：US15096786

申请日：2016-04-12

Applicant: Socionext Inc.

Inventor： Yuko Kodama

IPC: G06T3/40 ,  H04N5/232 ,  G06T5/00 ,  H04N5/247 ,  G06T7/33

Abstract: A drawing apparatus includes a first control unit and a second control unit. The first control unit receives a plurality of image data including a subject from a plurality of cameras, and outputs data obtained from coordinate conversion performed by referring to LUT data. The second control unit derives each of determination distances from optical centers of the plurality of image data with regard to the subject, selects one of the plurality of image data as selection image data on the basis of the determination distance, and rewrites the LUT data by deriving a coordinate corresponding to a pixel of the subject in the selection image data.

公开(公告)号：US20190244949A1

公开(公告)日：2019-08-08

申请号：US16386116

申请日：2019-04-16

Applicant: SOCIONEXT INC.

Inventor： Junji IWAHORI

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/0886 ,  H01L27/11803 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/11881

Abstract: A semiconductor integrated circuit device includes a standard cell having a plurality of height regions. A plurality of partial circuits having an identical function and each operating in response to common signals S and NS are arranged in any one of the height regions. A metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits, and a metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits.

公开(公告)号：US20190198530A1

公开(公告)日：2019-06-27

申请号：US16287907

申请日：2019-02-27

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/0207 ,  H01L27/04 ,  H01L27/092 ,  H01L29/78 ,  H01L2027/11812 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11892

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.