公开(公告)号：US20050029603A1

公开(公告)日：2005-02-10

申请号：US10633504

申请日：2003-08-05

Applicant: Bin Yu ,  Shibly Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly Ahmed ,  Haihong Wang

IPC: H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.

Abstract translation: 半导体器件可以包括衬底和形成在衬底上的绝缘层。 第一器件可以形成在绝缘层上，包括第一鳍片。 第一翅片可以形成在绝缘层上，并且可以具有第一翅片长宽比。 第二装置可以形成在绝缘层上，包括第二鳍片。 第二翅片可以形成在绝缘层上，并且可以具有与第一翅片长宽比不同的第二翅片长宽比。

公开(公告)号：US06852576B2

公开(公告)日：2005-02-08

申请号：US10825175

申请日：2004-04-16

Applicant: Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method forms fin structures for a semiconductor device. The method includes forming a first fin structure including a dielectric material and including a first side surface and a second side surface; forming a second fin structure adjacent the first side surface of the first fin structure; and forming a third fin structure adjacent the second side surface of the first fin structure. The second fin structure and the third fin structure are formed of a different material than the first fin structure.

Abstract translation: 一种形成半导体器件的鳍结构的方法。 该方法包括形成包括电介质材料并包括第一侧表面和第二侧表面的第一鳍结构; 在所述第一翅片结构的第一侧表面附近形成第二鳍结构; 以及在所述第一翅片结构的所述第二侧表面附近形成第三鳍​​结构。 第二翅片结构和第三翅片结构由与第一翅片结构不同的材料形成。

公开(公告)号：US06833588B2

公开(公告)日：2004-12-21

申请号：US10274867

申请日：2002-10-22

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC: H01L2701

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.

公开(公告)号：US06800885B1

公开(公告)日：2004-10-05

申请号：US10385652

申请日：2003-03-12

Applicant: Judy Xilin An ,  Bin Yu

Inventor： Judy Xilin An ,  Bin Yu

IPC: H01L2980

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7856

Abstract: An asymmetric double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a first fin formed on a substrate; a second fin formed on the substrate; a first gate formed adjacent first sides of the first and second fins, the first gate being doped with a first type of impurity; and a second gate formed between second sides of the first and second fins, the second gate being doped with a second type of impurity. An asymmetric all-around gate MOSFET includes multiple fins; a first gate structure doped with a first type of impurity and formed adjacent a first side of one of the fins; a second gate structure doped with the first type of impurity and formed adjacent a first side of another one of the fins; a third gate structure doped with a second type of impurity and formed between two of the fins; and a fourth gate structure formed at least partially beneath one or more of the fins.

Abstract translation: 非对称双栅极金属氧化物半导体场效应晶体管（MOSFET）包括在基板上形成的第一鳍片; 在所述基板上形成的第二翅片; 形成在所述第一和第二鳍片的第一侧附近的第一栅极，所述第一栅极掺杂有第一类型的杂质; 以及形成在所述第一和第二鳍片的第二侧之间的第二栅极，所述第二栅极掺杂有第二类型的杂质。 非对称全栅极MOSFET包括多个鳍片; 掺杂有第一类型杂质的第一栅极结构，并且邻近其中一个鳍片的第一侧形成; 掺杂有第一类型杂质的第二栅极结构，并且与另一个鳍片的第一侧相邻地形成; 掺杂有第二类杂质并形成在两个鳍之间的第三栅极结构; 以及至少部分地在一个或多个翅片下方形成的第四门结构。

公开(公告)号：US06787476B1

公开(公告)日：2004-09-07

申请号：US10632989

申请日：2003-08-04

Applicant: Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L21302

CPC classification number: H01L29/785 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/4908 ,  H01L29/66795

Abstract: A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third layer over the second layer. The third layer includes an anti-reflective coating. The method also includes etching the first, second and third layers to form the gate for the FinFET.

Abstract translation: 提供了一种形成Fin场效应晶体管（FinFET）的栅极的方法。 该方法包括在翅片上形成第一层材料，并在第一层上形成第二层。 第二层包括Ti或TiN。 该方法还包括在第二层上形成第三层。 第三层包括抗反射涂层。 该方法还包括蚀刻第一，第二和第三层以形成用于FinFET的栅极。

公开(公告)号：US06753182B1

公开(公告)日：2004-06-22

申请号：US08780449

申请日：1997-01-08

Applicant: Prakash G. Kadkade ,  Christopher B. Bare ,  Barbara Schnabel-Preikstas ,  Bin Yu

Inventor： Prakash G. Kadkade ,  Christopher B. Bare ,  Barbara Schnabel-Preikstas ,  Bin Yu

IPC: C12N104

CPC classification number: A01N3/00

Abstract: Methods are provided for cryopreserving plant cells and to methods for recovering viable plant cells from long or short term cryopreservation. Plant cells to be cryopreserved can be grown in culture and pretreated with a solution containing an cryorotective agent and a stabilizer. Pretreated cells are acclimated to a reduced temperature and loaded with a cryoprotective agent such as DMSO, propylene glycol or polyethylene glycol. Loaded cells are incubated with a vitrification solution which, for example, comprises a solution with a high concentration of the cryoprotective agent. Vitrified cells retain less than about 20% water content and can be frozen at cryopreservation temperatures for long periods of time without significantly altering the genotypic or phenotypic character of the cells. Plant cells may also be cryopreserved by lyophilizing cells to a preferable water content of about 40% to about 60% by weight prior to exposure to a vitrification solution or loading agent. The combination of lyophilization and vitrification or loading removes about 75% to about 95% of the plant cell's water. Cells can be successfully cryopreserved for long periods of time and viably recovered. Also provided are methods for the recovery of viable plant cells from cryopreservation. Cells are thawed to about room temperature and incubated in medium containing, a cryoprotective agent and a stabilizer. The cryoprotective agent is removed and the cells successfully incubated and recovered in liquid or semi-solid growth medium.

Abstract translation: 提供用于冷冻保存植物细胞的方法和用于从长期或短期冷冻保存中回收活的植物细胞的方法。 待冷冻保存的植物细胞可以在培养物中生长并用含有冷冻保护剂和稳定剂的溶液预处理。 预处理的细胞适应于降低的温度，并加载冷冻保护剂如DMSO，丙二醇或聚乙二醇。 将加载的细胞与玻璃化溶液一起孵育，所述玻璃化溶液例如包含具有高浓度冷冻保护剂的溶液。 玻璃化细胞保留少于约20％的水含量，并且可以在冷冻保存温度下长时间冷冻，而不显着改变细胞的基因型或表型特征。 在暴露于玻璃化溶液或加载剂之前，植物细胞还可以通过冻干细胞冷冻保存至约40％至约60％重量的优选水含量。 冷冻干燥和玻璃化或加载的组合去除植物细胞水的约75％至约95％。 细胞可以成功地冷冻保存长时间，有效地恢复。 还提供了从冷冻保存中回收活的植物细胞的方法。 将细胞解冻至约室温，并在含有冷冻保护剂和稳定剂的培养基中孵育。 除去冷冻保护剂，并将细胞在液体或半固体生长培养基中成功培养和回收。

公开(公告)号：US06706614B1

公开(公告)日：2004-03-16

申请号：US10145953

申请日：2002-05-15

Applicant: Judy Xilin An ,  Bin Yu

Inventor： Judy Xilin An ,  Bin Yu

IPC: H01L2176

CPC classification number: H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

Abstract: A silicon-on-insulator(SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hereto junction along a lower portion of the source/body junction.

Abstract translation: 绝缘体上硅（SOI）晶体管。 具有源极和漏极的SOI晶体管具有设置在其间的主体，源被注入锗以形成邻近源极的下部的源极/主体结的硅 - 锗的区域，硅 - 锗的面积 源沿着源/体结的下部形成本结。

公开(公告)号：US06706571B1

公开(公告)日：2004-03-16

申请号：US10274951

申请日：2002-10-22

Applicant: Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

Inventor： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78684

Abstract: A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures.

Abstract translation: 在半导体器件中形成多个结构的方法包括在导电层上沉积膜，蚀刻膜的一部分中的沟槽并且形成在沟槽的侧壁附近。 然后可以对该膜进行蚀刻，然后进行导电层的形成以形成结构。

公开(公告)号：US06686248B1

公开(公告)日：2004-02-03

申请号：US09825658

申请日：2001-04-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/26586 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating a semiconductor device, involving: forming a gate stack on a substrate; depositing a material layer on the gate stack; etching the material layer, thereby forming a dielectric capsulate layer on the gate stack; forming a pair of shallow source/drain extensions in a first region of the substrate by implanting a plurality of first dopant ions at a tilt angle with a horizontal offset defined by a thickness of the dielectric capsulate layer; and forming at least one spacer on the dielectric capsulate layer; forming deep source/drain contact junctions in a second region of the substrate by vertically implanting a plurality of second dopant ions below the first region with no tilt and with a horizontal offset defined by a thickness of the at least one spacer.

Abstract translation: 一种制造半导体器件的方法，包括：在衬底上形成栅叠层; 在栅极堆叠上沉积材料层; 蚀刻材料层，从而在栅叠层上形成电介质封装层; 通过以与介电封装层的厚度限定的水平偏移的倾斜角度注入多个第一掺杂剂离子，在衬底的第一区域中形成一对浅源极/漏极延伸部分; 以及在介电封装层上形成至少一个间隔物; 通过在第一区域的下方垂直地注入多个第二掺杂剂离子并且没有由至少一个间隔物的厚度限定的水平偏移，在衬底的第二区域中形成深源/漏接触结。

公开(公告)号：US06657267B1

公开(公告)日：2003-12-02

申请号：US10163930

申请日：2002-06-06

Applicant: Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Bin Yu

Inventor： Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/517 ,  H01L21/2652 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device and method of fabrication are disclosed. The semiconductor device includes a liner composed of a high-K material. The liner has a portion separating a sidewall spacer from a gate and a portion separating the sidewall spacer from a layer of semiconductor material. The liner functions as an etch stop during formation of the sidewall spacer. The liner is removable by an etch process that has substantially no reaction with an isolation region formed in the layer of semiconductor material.

Abstract translation: 公开了半导体器件和制造方法。 半导体器件包括由高K材料构成的衬垫。 衬套具有将侧壁间隔物与栅极分离的部分和将侧壁间隔物与半导体材料层分离的部分。 衬垫在形成侧壁间隔物期间用作蚀刻停止。 衬里可以通过蚀刻工艺去除，该蚀刻工艺基本上不与半导体材料层中形成的隔离区域发生反应。