Abstract:
A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.
Abstract:
A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
Abstract:
A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by a channel stop layer.
Abstract:
A semiconductor device includes a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer. The first device may include a first fin formed on the insulating layer, a first dielectric layer formed on the first fin, and a partially silicided gate formed over a portion of the first fin and the first dielectric layer. A second device also may be formed on the insulating layer. The second device may include a second fin formed on the insulating layer, a second dielectric layer formed on the second fin, and a fully silicided gate formed over a portion of the second fin and the second dielectric layer.
Abstract:
The present invention relates to methods for cryopreserving plant cells and to methods for recovering viable plant cells from long or short term cryopreservation. Plant cells to be cryopreserved can be grown in culture and pretreated with a solution containing an cryoprotective agent and, optionally, a stabilizer. Stabilizers are preferably membrane stabilizers such as ethylene inhibitors, oxygen radical scavengers and divalent cations. Cells can also be stabilized by subjecting the culture to a heat shock. Pretreated cells are acclimated to a reduced temperature and loaded with a cryoprotective agent such as DMSO, propylene glycol or polyethylene glycol. Loaded cells are incubated with a vitrification solution which, for example, comprises a solution with a high concentration of the cryoprotective agent. Vitrified cells retain less than about 20% water content and can be frozen at cryopreservation temperatures for long periods of time without significantly altering the genotypic or phenotypic character of the cells. Plant cells may also be cryopreserved by lyophilizing cells prior to exposure to a vitrification solution. The combination of lyophilization and vitrification removes about 80% to about 95% of the plant cell's water. Cells can be successfully cryopreserved for long periods of time and viably recovered. The invention also relates to methods for the recovery of viable plant cells from cryopreservation. Cells are thawed to about room temperature and incubated in medium containing a cryoprotective agent and a stabilizer. The cryoprotective agent is removed and the cells successfully incubated and recovered in liquid or semi-solid growth medium. The invention also relates to the cryopreserved cells and to viable plant cells which have been recovered from long or short term cryopreservation.
Abstract:
A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by an insulating layer.
Abstract:
A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
Abstract:
A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.
Abstract:
A method forms fin structures for a semiconductor device. The method includes forming a first fin structure including a dielectric material and including a first side surface and a second side surface; forming a second fin structure adjacent the first side surface of the first fin structure; and forming a third fin structure adjacent the second side surface of the first fin structure. The second fin structure and the third fin structure are formed of a different material than the first fin structure.
Abstract:
A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.