公开(公告)号：US20100168880A1

公开(公告)日：2010-07-01

申请号：US12457805

申请日：2009-06-22

Applicant: Chien-Hung Liu ,  Chi-Chen Cheng

Inventor： Chien-Hung Liu ,  Chi-Chen Cheng

IPC: G06F17/00 ,  G06Q40/00 ,  G06Q30/00 ,  G06Q20/00 ,  G06Q50/00 ,  G05B19/00

CPC classification number: G07F17/30 ,  G06Q20/105 ,  G06Q20/123 ,  G06Q20/363 ,  G06Q30/06 ,  G06Q30/0601 ,  G07F17/16

Abstract: An apparatus of combined an online music player and a chip card reader, and an online payment system and the method are disclosed. Particularly, a network-platform agent program is employed to activate an online music playing unit and a chip card reading unit disposed inside the apparatus. The apparatus provides the chip card reader an environment linking to network, so the user may use the chip card with deposit of money to process online trade and payment through the chip card reading unit. It is featured that no further user authentication or transmission of personal data is required. According to the preferred embodiment, the apparatus of combined online music player and chip card reader are provided to link to a network information service platform via the agent program. Therefore, the invention provides an easy way for the user using the apparatus to process the trade and payment on the platform.

Abstract translation: 公开了一种组合在线音乐播放器和芯片读卡器的装置，以及在线支付系统和方法。 特别地，使用网络平台代理程序来激活设置在设备内部的在线音乐播放单元和芯片卡读取单元。 该装置为芯片读卡器提供链接到网络的环境，因此用户可以使用具有存款的芯片卡来通过芯片卡读取单元处理在线交易和支付。 它的特点是不需要进一步的用户认证或传输个人数据。 根据优选实施例，提供组合在线音乐播放器和芯片卡读卡器的装置，以通过代理程序链接到网络信息服务平台。 因此，本发明提供了一种使用该装置的用户在平台上处理交易和支付的简单方法。

公开(公告)号：US07652324B2

公开(公告)日：2010-01-26

申请号：US11655259

申请日：2007-01-19

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: H01L29/94

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7923

Abstract: A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.

Abstract translation: 提供NAND型双位氮化物只读存储器及其制造方法。 首先，在衬底中形成彼此间隔开并平行的多个隔离层。 接下来，在基板上形成多个字线和多个氧化物 - 氮化物 - 氧化物（ONO）堆叠结构。 字线彼此间隔开并平行，字线也垂直于隔离层。 每个ONO堆叠结构位于相应的字线和基板之间。 然后在衬底上形成位于字线之间和隔离层之间的多个不连续位线。 本发明的NAND型双位氮化物只读存储器的结构类似于互补金属氧化物半导体（CMOS）的结构，并且它们的制造工艺是完全兼容的。

公开(公告)号：US07635814B2

公开(公告)日：2009-12-22

申请号：US11941979

申请日：2007-11-19

Applicant: Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

Inventor： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  Y10S439/941

Abstract: A printed circuit board (PCB) includes first and second signal layers sandwiching a dielectric layer therebetween and a first differential pair and a second differential pair each having a positive differential trace and a negative differential trace. The positive differential traces of the two differential pairs are disposed within the first signal layer. The negative differential traces of the two differential pairs are disposed within the second signal layer. The positive differential trace of the first differential pair is defined at the left side of the positive differential trace of the second differential pair. The negative differential trace of the first differential pair is defined at the right side of the negative differential trace of the second differential pair.

Abstract translation: 印刷电路板（PCB）包括夹在其间的电介质层的第一和第二信号层，以及分别具有正差分迹线和负差分迹线的第一差分对和第二差分对。 两个差分对的正差分迹线设置在第一信号层内。 两个差分对的负差分迹线设置在第二信号层内。 第一差分对的正差分迹线被定义在第二差分对的正差分迹线的左侧。 第一差分对的负差分迹线被限定在第二差分对的负差分迹线的右侧。

公开(公告)号：US07612631B2

公开(公告)日：2009-11-03

申请号：US11942727

申请日：2007-11-20

Applicant: Shou-Kuo Hsu ,  Chien-Hung Liu ,  Cheng-Shien Li

Inventor： Shou-Kuo Hsu ,  Chien-Hung Liu ,  Cheng-Shien Li

IPC: H03H2/00 ,  H01P1/10

CPC classification number: G06F13/409

Abstract: A motherboard includes a signal control chip, a signal switch chip connected to the signal control chip via a plurality of first transmission lines, and a complex connector configured for connecting to a first type of transmission device or a second type of transmission device. The signal control chip is connected to the complex connector via the first transmission lines and a plurality of second transmission lines. The signal switch chip is electrically connected to the complex connector via a plurality of third transmission lines. Each second transmission line is connected in series with a first resistor. Each third transmission line is connected in series with a second resistor. When the first type of transmission device is mounted on the complex connector, the signal switch chip and the second resistors are removed. When the second type of transmission device is mounted on the complex connector, the first resistors are removed.

Abstract translation: 主板包括信号控制芯片，经由多个第一传输线连接到信号控制芯片的信号开关芯片，以及被配置为连接到第一类型的传输设备或第二类型的传输设备的复合连接器。 信号控制芯片通过第一传输线和多条第二传输线连接到复合连接器。 信号开关芯片通过多条第三传输线与复合连接器电连接。 每个第二传输线与第一电阻器串联连接。 每个第三传输线与第二电阻器串联连接。 当第一类型的传输装置安装在复合连接器上时，信号开关芯片和第二电阻器被去除。 当第二种类型的传输装置安装在复合连接器上时，第一电阻被去除。

公开(公告)号：US07576425B2

公开(公告)日：2009-08-18

申请号：US11657734

申请日：2007-01-25

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: H01L23/12

CPC classification number: H01L27/14618 ,  H01L24/16 ,  H01L25/042 ,  H01L27/14683 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A conducting layer in a chip package module includes one or a plurality of through hole penetrating the top of a base being disposed at the bottom of an insulating layer in the chip package module, and inner wall of the through hole being applied with insulation material so that the conductive layer subsequently constructed to the peripheral of the insulation layer may pass the through hole to extend to where above the base before construction of a masking layer and multiple circuit pins to complete construction of the conducting layer that is totally enveloped so to prevent easy oxidization at the conducting layer and improve stability of the chip package to avoid breaking up due to external force applied.

Abstract translation: 芯片封装模块中的导电层包括穿过基片顶部的一个或多个通孔，其设置在芯片封装模块中的绝缘层的底部，并且通孔的内壁被施加绝缘材料 随后构造到绝缘层的周边的导电层可以在构造掩模层和多个电路引脚之前通过通孔延伸到基底之上，以完成包封的导电层的构造，从而防止容易 导电层氧化，提高芯片封装的稳定性，避免施加外力而导致断裂。

公开(公告)号：US20080169556A1

公开(公告)日：2008-07-17

申请号：US11653425

申请日：2007-01-16

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: H01L23/34

CPC classification number: H01L23/3677 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat sink mechanism including multiple heat passages in the base of a casing of a chip package module penetrating through a substrate packed in the module; a metal material being deposited in each heat passage to become a heat sink conductor connecting the substrate and the surface of the casing to effectively solve the problem of excessive heat generated in the course of HF operation of the chip package module thus to prevent chip failure.

Abstract translation: 一种散热机构，包括穿过包装在所述模块中的基板的芯片封装模块的壳体的底部中的多个热通道; 沉积在每个热通道中的金属材料成为连接衬底和壳体表面的散热导体，以有效地解决芯片封装模块的HF操作过程中产生的过多热量的问题，从而防止芯片故障。

公开(公告)号：US07307018B2

公开(公告)日：2007-12-11

申请号：US11236961

申请日：2005-09-27

Applicant: Jui-Pin Chang ,  Chien-Hung Liu ,  Ying-Tso Chen ,  Shou-Wei Huang

Inventor： Jui-Pin Chang ,  Chien-Hung Liu ,  Ying-Tso Chen ,  Shou-Wei Huang

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L23/5283 ,  H01L21/76834 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.

Abstract translation: 形成适于降低导线的薄层电阻的导线的方法。 该方法包括提供其上形成有导电层的材料层并在导电层上形成图案化掩模层的步骤。 此外，通过使用图案化掩模层作为掩模去除导电层的一部分，并且在图案化掩模层和导电层的侧壁上形成间隔物。 导电层的一部分被去除直到材料层暴露以形成导电线，其中间隔物和图案化掩模层用作掩模。

公开(公告)号：US20060286731A1

公开(公告)日：2006-12-21

申请号：US11236961

申请日：2005-09-27

Applicant: Jui-Pin Chang ,  Chien-Hung Liu ,  Ying-Tso Chen ,  Shou-Wei Huang

Inventor： Jui-Pin Chang ,  Chien-Hung Liu ,  Ying-Tso Chen ,  Shou-Wei Huang

IPC: H01L21/8234 ,  H01L21/44 ,  H01L23/52

CPC classification number: H01L23/5283 ,  H01L21/76834 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.

Abstract translation: 形成适于降低导线的薄层电阻的导线的方法。 该方法包括提供其上形成有导电层的材料层并在导电层上形成图案化掩模层的步骤。 此外，通过使用图案化掩模层作为掩模去除导电层的一部分，并且在图案化掩模层和导电层的侧壁上形成间隔物。 导电层的一部分被去除直到材料层暴露以形成导电线，其中间隔物和图案化掩模层用作掩模。

公开(公告)号：US07108961B2

公开(公告)日：2006-09-19

申请号：US10702555

申请日：2003-11-07

Applicant: Chi-Ming Huang ,  Chia-Tai Chen ,  Yu-Hung Chuang ,  Jian-Chiun Lion ,  Chien-Hung Liu ,  Chun-Jung Chen

Inventor： Chi-Ming Huang ,  Chia-Tai Chen ,  Yu-Hung Chuang ,  Jian-Chiun Lion ,  Chien-Hung Liu ,  Chun-Jung Chen

IPC: B41J2/16

CPC classification number: B41J2/16 ,  B41J2/1625 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2/1639 ,  H05K3/0023 ,  H05K3/205 ,  H05K2201/09063 ,  H05K2201/0969

Abstract: A component for the inkjet print head and the manufacturing method thereof are disclosed where photosensitive polymer is used as the substrate. Orifices and ink chambers are made on the substrate by photolithography. Conductive traces for interconnection to a print head chip are integrated to the substrate by combining photolithography and electroforming procedures.

Abstract translation: 公开了一种用于喷墨打印头的部件及其制造方法，其中使用光敏聚合物作为基底。 通过光刻在基板上制造孔和墨室。 用于与打印头芯片互连的导电迹线通过组合光刻和电铸工艺而集成到衬底中。

公开(公告)号：US20060001078A1

公开(公告)日：2006-01-05

申请号：US11171353

申请日：2005-07-01

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7923

Abstract: A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.

Abstract translation: 提供NAND型双位氮化物只读存储器及其制造方法。 首先，在衬底中形成彼此间隔开并平行的多个隔离层。 接下来，在基板上形成多个字线和多个氧化物 - 氮化物 - 氧化物（ONO）堆叠结构。 字线彼此间隔开并平行，字线也垂直于隔离层。 每个ONO堆叠结构位于相应的字线和基板之间。 然后，在基板上形成位于字线之间和隔离层之间的多个不连续位线。 本发明的NAND型双位氮化物只读存储器的结构类似于互补金属氧化物半导体（CMOS）的结构，并且它们的制造工艺是完全兼容的。