公开(公告)号：US06316277B1

公开(公告)日：2001-11-13

申请号：US09580612

申请日：2000-05-30

申请人： Khoi A. Phan ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Jeff Schefske

发明人： Khoi A. Phan ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Jeff Schefske

IPC分类号： H01L2166

CPC分类号： H01L22/24

摘要： There is provided a method for enhancing the contrast between oxide film and ultra-thin resists in deep-ultraviolet lithography for use with a wafer defect inspection system in order to maximize defect inspection sensitivity. This is achieved by varying the thickness of the oxide film for a given ultra-thin resist thickness so as to produce a high contrast. As a result, defect inspection of the ultra-thin resist pattern is easily obtained. In a second embodiment, the ultra-thin resist thickness is varied for a given oxide film thickness. In a third embodiment, both the oxide film and the ultra-thin resist thicknesses are varied simultaneously so as to obtain an optimum contrast.

摘要翻译： 提供了一种用于在深紫外线光刻中增强氧化膜和超薄抗蚀剂之间的对比度以与晶片缺陷检查系统一起使用以便最大化缺陷检查灵敏度的方法。 这是通过改变给定的超薄抗蚀剂厚度的氧化膜的厚度来实现的，以产生高对比度。 结果，容易获得超薄抗蚀剂图案的缺陷检查。 在第二实施例中，对于给定的氧化膜厚度，超薄抗蚀剂厚度是变化的。 在第三实施例中，氧化膜和超薄抗蚀剂厚度同时变化，以获得最佳对比度。

公开(公告)号：US06214737B1

公开(公告)日：2001-04-10

申请号：US09234379

申请日：1999-01-20

申请人： Christopher F. Lyons ,  Michael K. Templeton ,  Kathleen R. Early

发明人： Christopher F. Lyons ,  Michael K. Templeton ,  Kathleen R. Early

IPC分类号： H01L213065

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76838

摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a mask over a first portion of the conductive film wherein a second portion of the conductive film is exposed; partially etching the second portion of the conductive film thereby forming a sidewall in the conductive film; removing the mask; depositing a sidewall film over the conductive film, the sidewall film having a vertical portion adjacent the sidewall of the conductive film and a horizontal portion in areas not adjacent the sidewall of the conductive film; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; and etching the third portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.

摘要翻译： 在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在导电膜的第一部分上图案化掩模，其中导电膜的第二部分被暴露; 部分蚀刻导电膜的第二部分，从而在导电膜中形成侧壁; 去除面膜; 在所述导电膜上沉积侧壁膜，所述侧壁膜具有邻近所述导电膜的侧壁的垂直部分和在不邻近所述导电膜的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 并且蚀刻导电膜的第三部分，从而提供具有在侧壁膜的垂直部分下方的约100nm或更小的宽度的导电结构。

公开(公告)号：US06200907B1

公开(公告)日：2001-03-13

申请号：US09204216

申请日：1998-12-02

申请人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

发明人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

IPC分类号： H01L21302

CPC分类号： H01L21/32139 ,  H01L21/0275 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76838

摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

摘要翻译： 在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的阻挡金属层; 在阻挡金属层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂具有小于约的厚度; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 显影暴露一部分阻挡金属层的超薄光刻胶; 蚀刻暴露部分氧化物层的阻挡金属层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

公开(公告)号：US06184128B2

公开(公告)日：2001-02-06

申请号：US09497222

申请日：2000-01-31

申请人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

发明人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

IPC分类号： H01L214763

CPC分类号： H01L21/7681 ,  H01L21/31144

摘要： In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second photoresist have a thickness of about 1,500 Å or less.

摘要翻译： 在一个实施例中，本发明涉及一种双镶嵌方法，包括以下步骤：提供具有第一低k材料层的基底; 在所述第一低k材料层上形成第一硬掩模层; 使用第一光致抗蚀剂构图在第一硬掩模层中具有第一宽度的第一开口，从而暴露第一低k材料层的一部分; 去除第一光致抗蚀剂; 在图案化的第一硬掩模层和第一低k材料层的暴露部分上沉积第二低k材料层; 在所述第二低k材料层上形成第二硬掩模层; 使用第二光致抗蚀剂构图在第二硬掩模层中形成具有大于第一宽度的宽度的第二开口，从而暴露第二低k材料层的一部分; 各向异性地蚀刻第一和第二低k材料层的暴露部分; 并且去除所述第二光致抗蚀剂，其中所述第一光致抗蚀剂和所述第二光致抗蚀剂中的至少一个具有大约等于或小于1500埃的厚度。

公开(公告)号：US06171962B2

公开(公告)日：2001-01-09

申请号：US08993889

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21302

CPC分类号： H01L21/76229 ,  H01L21/31053

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized. Since the insulating material is partially planarized by the first polish and the seams and steps are filled by the second deposition, the resulting topography of the upper surface of the second layer of insulating material is small enough to enable a direct final polish without the need to create and implement a planarization mask and to perform an etch and mask removal, thereby reducing manufacturing costs and increasing production throughput.

摘要翻译： 在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构，而不需要平坦化掩模或蚀刻。 实施例包括用绝缘材料形成沟槽并再填充它们，该绝缘材料也覆盖衬底表面，接着进行抛光以除去绝缘材料的上部并使小沟槽上方的绝缘材料平坦化。 然后沉积第二层绝缘材料以填充小沟槽上方的绝缘材料中的接缝，并填充大沟槽上方的绝缘材料的步骤。 然后将绝缘材料平坦化。 由于绝缘材料被第一抛光部分地平坦化并且接缝和步骤通过第二次沉积来填充，所以第二层绝缘材料的上表面的所得形貌足够小以使得能够进行直接的最终抛光，而不需要 创建并实现平面化掩模并执行蚀刻和掩模去除，从而降低制造成本并提高生产量。

公开(公告)号：US6130467A

公开(公告)日：2000-10-10

申请号：US993857

申请日：1997-12-18

申请人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L21/762 ,  H01L29/00

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure is formed in a semiconductor substrate with an oxide or nitride spacer overlying and protecting a portion of a pad oxide layer at the trench edge such that the pad oxide layer acts as part of the gate oxide layer. Embodiments include providing a step between the trench fill and the pad oxide layer and forming the protective spacer thereon. The protective spacer protects the underlying portion of the pad oxide layer at the trench edge during pad oxide removal prior to forming a gate oxide. Therefore, it is only necessary to grow the gate oxide on the main surface of the substrate, not at the trench edges. The gate oxide can then be formed uniformly thin, while the remaining pad oxide at the trench edges is relatively thick.

摘要翻译： 在具有氧化物或氮化物间隔物的半导体衬底中形成绝缘沟槽隔离结构，覆盖并保护沟槽边缘处的焊盘氧化物层的一部分，使得焊盘氧化物层用作栅极氧化物层的一部分。 实施例包括在沟槽填充物和衬垫氧化物层之间提供步骤，并在其上形成保护隔离物。 在形成栅极氧化物之前，保护间隔物在衬垫氧化物去除期间保护焊盘氧化物层的沟槽边缘的下面部分。 因此，仅需要在衬底的主表面上而不是在沟槽边缘处生长栅极氧化物。 然后可以将栅极氧化物均匀地形成，而沟槽边缘处的剩余焊盘氧化物相对较厚。

公开(公告)号：US6090713A

公开(公告)日：2000-07-18

申请号：US992491

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyophadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyophadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/316

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L21/31055

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, depositing a second, thin layer of insulating material filling seams in the insulating material above the small trenches, masking the insulating material above the large trenches, isotropically etching, and polishing to planarize the insulating material. Since the insulating material is partially planarized and the seams over the small trenches are filled, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask having relatively few features with relatively large geometry avoids the necessity of creating and implementing a complex, critical mask, thereby reducing manufacturing costs and increasing production throughput.

摘要翻译： 使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成沟槽并用也覆盖衬底表面的绝缘材料再填充它们，抛光以去除绝缘材料的上部并平面化小沟槽上方的绝缘材料，沉积第二薄层的绝缘材料填充接缝 在小沟槽上方的绝缘材料中，掩蔽大沟槽上方的绝缘材料，各向同性蚀刻和抛光以使绝缘材料平坦化。 由于绝缘材料被部分平坦化并且填充了小沟槽上的接缝，所以可以在仅在大沟槽而不是小沟槽上形成相对简单的平坦化掩模之后进行蚀刻。 使用具有相对较小几何特征的平面化掩模具有相对大的几何形状避免了创建和实施复杂的关键掩模的必要性，从而降低制造成本并提高生产量。

公开(公告)号：US5990524A

公开(公告)日：1999-11-23

申请号：US993868

申请日：1997-12-18

申请人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

发明人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

IPC分类号： H01L21/768 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.

摘要翻译： 在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底， 更重叠的电介质层。 穿通区域可能会损坏晶体管电路。 提供改进的多用途间隔件以减少过度蚀刻的机会。 多用途间隔件由硅肟制成。 用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。 此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。

公开(公告)号：US5963841A

公开(公告)日：1999-10-05

申请号：US924370

申请日：1997-09-05

申请人： Olov B. Karlsson ,  Christopher F. Lyons ,  Minh Van Ngo ,  Scott A. Bell ,  David K. Foote

发明人： Olov B. Karlsson ,  Christopher F. Lyons ,  Minh Van Ngo ,  Scott A. Bell ,  David K. Foote

IPC分类号： H01L21/3213 ,  H01L21/302

CPC分类号： H01L21/32139

摘要： A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.

摘要翻译： 通过使用底部抗反射涂层（BARC）在半导体衬底上形成栅极以更好地控制通过形成在其上的深UV抗蚀剂掩模所限定的栅极的临界尺寸（CD）。 晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层，导电层上的SiON BARC，SiON BARC上的薄氧化物膜。 在氧化物膜上形成抗蚀剂掩模。 SiON BARC改进了抗蚀剂掩模形成过程。 然后通过依次蚀刻通过抗蚀剂掩模中由蚀刻窗口限定的氧化膜，BARC和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。 一旦适当成形，就去除了抗蚀剂掩模，氧化膜和SiON BARC的其余部分。

公开(公告)号：US5930645A

公开(公告)日：1999-07-27

申请号：US993881

申请日：1997-12-18

申请人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok

发明人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： An insulated trench isolation structure is formed in a semiconductor substrate using a thin amorphous silicon or polysilicon polish stop layer by adding a reflectance compensation layer on the polish stop layer. As a result, the topological step between the main surface of the substrate and the uppermost surface of the trench fill is reduced, thereby facilitating the application and enhancing the accuracy of photolithographic techniques in forming features with minimal dimensions.

摘要翻译： 通过在抛光停止层上添加反射率补偿层，在半导体衬底中使用薄的非晶硅或多晶硅抛光停止层形成绝缘沟槽隔离结构。 结果，衬底的主表面和沟槽填充物的最上表面之间的拓扑步骤减少，从而有助于在最小尺寸形成特征时光刻技术的应用和提高精度。