公开(公告)号：US10903142B2

公开(公告)日：2021-01-26

申请号：US16402482

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Tat Hin Tan ,  Wai Ling Lee

IPC: H01L23/02 ,  H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822 ,  H01L49/02

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US10886209B2

公开(公告)日：2021-01-05

申请号：US16326544

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Stephen Harvey Hall ,  Bok Eng Cheah ,  Chaitanya Sreerama ,  Jackson Chung Peng Kong

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48

Abstract: A self-equalizing interconnect in a connector is installed in a microelectronic device. The self-equalizing interconnect is formed of a plurality of electrically conductive layers under conditions to offset skin-effect losses with respect to frequency change during operation. Each successive layer is configured to with the next highest electrical conductivity and subsequent electrically conductive films gradually decrease in electrical conductivity. In an embodiment, thickness of the conductive film adjacent the reference plain is configured thinnest and subsequent films are added and are seriatim gradually thicker. The highest electrically conductive film is configured closest to a reference plane in the connector, and the lowest electrically conductive film is farthest from the reference plane.

公开(公告)号：US20200325711A1

公开(公告)日：2020-10-15

申请号：US16859452

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/3218 ,  G06F1/3234 ,  E05D11/00 ,  H05K5/02

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

公开(公告)号：US20200083157A1

公开(公告)日：2020-03-12

申请号：US16469100

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  J-Wing Teh ,  Bok Eng Cheah

IPC: H01L23/525 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L27/02

Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.

公开(公告)号：US20190311978A1

公开(公告)日：2019-10-10

申请号：US16280850

申请日：2019-02-20

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Ping Ping Ooi ,  Shaw Fong Wong ,  Jackson Chung Peng Kong ,  Hungying Lo

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/00 ,  H01L25/16 ,  H01L21/48 ,  H05K3/34

Abstract: A semiconductor package substrate includes a composite and stacked vertical interconnect on a land side of the substrate. The composite and stacked vertical interconnect includes a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

公开(公告)号：US20190304885A1

公开(公告)日：2019-10-03

申请号：US16279656

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kool Chi Ooi ,  Yang Liang Poh

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

公开(公告)号：US10334736B2

公开(公告)日：2019-06-25

申请号：US15795189

申请日：2017-10-26

Applicant: Intel Corporation

Inventor： Boon Ping Koh ,  Bok Eng Cheah

IPC: H05K1/00 ,  H05K1/18 ,  H01Q1/38 ,  H01Q1/22 ,  H01Q9/28 ,  H01L23/00 ,  H05K1/16

Abstract: A flexible integrated circuit that includes a first dielectric layer having a first section at one polarity and a second section at an opposing polarity, wherein the first section and the second section are separated by dielectric material within first dielectric layer; a second dielectric layer having a first side wall that is electrically connected to the first section and a second side wall that is electrically connected to the second section; and a third dielectric layer having a base that is electrically connected to the first side wall and the second side wall, wherein the second dielectric layer is between the first dielectric layer and the third dielectric layer, wherein the base, the first and second side walls and the first and second sections form an antenna that is configured to send or receive wireless signals.

公开(公告)号：US10319698B2

公开(公告)日：2019-06-11

申请号：US15354291

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A microelectronic device package including multiple layers of stacked die. Multiple die layers in the package can include two or more die. At least two die in a first layer will be laterally spaced from one another to define a first gap extending in a first direction; and at least two die in a second layer will be laterally spaced from one another to define a second gap extending in a second direction that is angularly offset from the first direction. The first and second directions can be perpendicular to one another.

公开(公告)号：US20190103359A1

公开(公告)日：2019-04-04

申请号：US15845382

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Paik Wen Ong

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18 ,  H01L25/16

Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.

公开(公告)号：US20180350748A1

公开(公告)日：2018-12-06

申请号：US15778379

申请日：2015-11-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Stephen Harvey Hall ,  Khang Choong Yong ,  Kooi Chi Ooi ,  Eric C Gantner

IPC: H01L23/538 ,  H01L23/66 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/561 ,  H01L21/565 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5387 ,  H01L23/5389 ,  H01L23/66 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2223/6638 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/189

Abstract: An electrical interconnect for an electronic package. The electrical interconnect includes a first dielectric layer; a second dielectric layer; a signal conductor positioned between the first dielectric layer and the second dielectric layer; and a conductive reference layer mounted on the first dielectric layer, and wherein the conductive reference layer does not cover the signal conductor. The conductive reference layer may be a first conductive reference layer and the electrical interconnect further comprises a second conductive reference layer mounted on the second dielectric layer. The second conductive reference layer does not cover the signal conductor. In addition, the signal conductor may be a first signal conductor and the electrical interconnect may further include a second signal conductor between the first dielectric layer and the second dielectric layer. The first and second signal conductors may form a differential pair of conductors.