公开(公告)号：US10580973B2

公开(公告)日：2020-03-03

申请号：US16214306

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  David L. Kencke ,  Robert S. Chau ,  Roksana Golizadeh Mojarad

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US10439134B2

公开(公告)日：2019-10-08

申请号：US15117594

申请日：2014-03-25

Applicant: INTEL CORPORATION

Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Uday Shah ,  Niloy Mukherjee ,  Charles C. Kuo ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L45/00 ,  H01L27/24

Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

公开(公告)号：US10411068B2

公开(公告)日：2019-09-10

申请号：US15767127

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  Kaan Oguz ,  Kevin P. O'Brien ,  Tofizur Rahman ,  Brian S. Doyle ,  Tahir Ghani ,  Mark L. Doczy

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: Disclosed herein are electrical contacts for magnetoresistive random access memory (MRAM) devices and related memory structures, devices, and methods. For example, and electrical contact for an MRAM device may include: a tantalum region; a barrier region formed of a first material; and a passivation region formed of a second material and disposed between the tantalum region and the barrier region, wherein the second material includes tantalum nitride and is different from the first material.

公开(公告)号：US10403811B2

公开(公告)日：2019-09-03

申请号：US15503680

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Robert S. Chau

IPC: G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US10388858B2

公开(公告)日：2019-08-20

申请号：US15503357

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Brian S. Doyle ,  Kaan Oguz ,  Robert S. Chau ,  Satyarth Suri

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10

Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.

公开(公告)号：US10365894B2

公开(公告)日：2019-07-30

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov

IPC: G06F7/58 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.

公开(公告)号：US10158065B2

公开(公告)日：2018-12-18

申请号：US15126682

申请日：2014-07-07

Applicant: INTEL CORPORATION

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  David L. Kencke ,  Robert S. Chau ,  Roksana Golizadeh Mojarad

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US20180323367A1

公开(公告)日：2018-11-08

申请号：US15735613

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Elijah V. Karpov ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Niloy Mukherjee ,  Prashant Majhi

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L45/00

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.

公开(公告)号：US20180254077A1

公开(公告)日：2018-09-06

申请号：US15755566

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Uday Shah ,  Ravi Pillarisetty ,  Brian S. Doyle

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14

CPC classification number: G11C11/161 ,  G11C11/14 ,  G11C11/1659 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/12

Abstract: An embodiment includes a memory array comprising: a memory cell including a switch stack in series with a memory stack; and a bit line above the memory cell and a word line below the memory cell; wherein (a) first switch stack sidewalls of the switch stack are vertically aligned with bit line sidewalls of the bit line and second switch stack sidewalls of the switch stack are vertically aligned with word line sidewalls of the word line; (b) first memory stack sidewalls of the memory stack are vertically aligned with the bit line sidewalls and second memory stack sidewalls of the memory stack are vertically aligned with the word line sidewalls. Other embodiments are described herein.

公开(公告)号：US20180240970A1

公开(公告)日：2018-08-23

申请号：US15755437

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3272 ,  H01F10/3286 ,  H01F41/307 ,  H01L43/08 ,  H01L43/10

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.