公开(公告)号：US10897009B2

公开(公告)日：2021-01-19

申请号：US16414956

申请日：2019-05-17

申请人： INTEL CORPORATION

发明人： Niloy Mukherjee ,  Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Ryan E Arch ,  Markus Kuhn ,  Justin S. Brockman ,  Huiying Liu ,  Elijah V Karpov ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： H01L45/00

摘要： Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

公开(公告)号：US10734513B2

公开(公告)日：2020-08-04

申请号：US15768822

申请日：2015-11-16

申请人： Intel Corporation

发明人： Prashant Majhi ,  Jack T. Kavalieros ,  Elijah V. Karpov ,  Uday Shah ,  Ravi Pillarisetty

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/267

摘要： Heterojunction tunnel field effect transistors (hTFETs) incorporating one or more oxide semiconductor and a band offset between at least one of a channel material, a source material of a first conductivity type, and drain of a second conductivity type, complementary to the first. In some embodiments, at least one of p-type material, channel material and n-type material comprises an oxide semiconductor. In some embodiments, two or more of p-type material, channel material, and n-type material comprises an oxide semiconductor. In some n-type hTFET embodiments, all of p-type, channel, and n-type materials are oxide semiconductors with a type-II or type-III band offset between the p-type and channel material.

公开(公告)号：US10706921B2

公开(公告)日：2020-07-07

申请号：US16080922

申请日：2016-04-01

申请人： INTEL CORPORATION

发明人： Elijah V. Karpov ,  Ravi Pillarisetty ,  Prashant Majhi ,  Niloy Mukherjee ,  Uday Shah

IPC分类号： G11C13/00 ,  H01L27/24

摘要： One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.

公开(公告)号：US10573809B2

公开(公告)日：2020-02-25

申请号：US16077571

申请日：2016-03-31

申请人： Intel Corporation

发明人： Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  Elijah V. Karpov ,  Niloy Mukherjee ,  Pulkit Jain ,  Aravind S. Killampalli ,  Jay P. Gupta ,  James S. Clarke

IPC分类号： H01L45/00

摘要： An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

公开(公告)号：US20190036020A1

公开(公告)日：2019-01-31

申请号：US16077571

申请日：2016-03-31

申请人： Intel Corporation

发明人： Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  Elijah V. Karpov ,  Niloy Mukherjee ,  Pulkit Jain ,  Aravind S. Killampalli ,  Jay P. Gupta ,  James S. Clarke

IPC分类号： H01L45/00

CPC分类号： H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1641

摘要： An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

公开(公告)号：US20180331288A1

公开(公告)日：2018-11-15

申请号：US15776845

申请日：2015-12-26

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Niloy Mukherjee ,  Elijah V. Karpov

IPC分类号： H01L45/00

CPC分类号： H01L45/1675 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

摘要： An embodiment includes a resistive random access memory (RRAM) comprising: top and bottom electrodes; first and second oxygen exchange layers (OELs) between the top and bottom electrodes; an oxide layer between the first and second OELs; wherein (a) first oxygen vacancies are within an upper third of the oxide layer at a first concentration, (b) second oxygen vacancies are within a lower third of the oxide layer at a second concentration, and (c) third oxygen vacancies are within a middle third of the oxide layer at a third concentration that is less than either of the first and second concentrations. Other embodiments are described herein.

公开(公告)号：US09871117B2

公开(公告)日：2018-01-16

申请号：US15062007

申请日：2016-03-04

申请人： Intel Corporation

发明人： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

IPC分类号： H01L31/072 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/205 ,  H01L29/739 ,  H01L29/749 ,  H01L21/02 ,  H01L21/306 ,  H01L29/49 ,  H01L29/161 ,  H01L29/201 ,  H01L29/08

CPC分类号： H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

摘要： Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

公开(公告)号：US09799759B2

公开(公告)日：2017-10-24

申请号：US15043935

申请日：2016-02-15

申请人： INTEL CORPORATION

发明人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

IPC分类号： H01L29/26 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778 ,  H01L21/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/15 ,  H01L29/51 ,  H01L29/165

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US09437808B2

公开(公告)日：2016-09-06

申请号：US14887168

申请日：2015-10-19

申请人： Intel Corporation

发明人： Brian S. Doyle ,  Charles C. Kuo ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Uday Shah

IPC分类号： G11C11/00 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C11/155 ,  G11C11/16 ,  H01L43/10

CPC分类号： H01L43/02 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.

公开(公告)号：US09263557B2

公开(公告)日：2016-02-16

申请号：US14069880

申请日：2013-11-01

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been-Yih Jin ,  Robert S. Chau

IPC分类号： H01L29/66 ,  B82Y10/00 ,  H01L29/267 ,  H01L29/775 ,  H01L29/778 ,  H01L21/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/51

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.