公开(公告)号：US11239248B2

公开(公告)日：2022-02-01

申请号：US16686830

申请日：2019-11-18

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  John D. Hopkins ,  Roger W. Lindsay ,  Shuangqiang Luo

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11529 ,  H01L21/768

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

公开(公告)号：US11239181B2

公开(公告)日：2022-02-01

申请号：US16662705

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Lifang Xu ,  Jian Li

IPC: H01L27/1157 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11529

Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.

公开(公告)号：US20210249433A1

公开(公告)日：2021-08-12

申请号：US16784435

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Vinayak Shamanna ,  Lifang Xu ,  Aaron R. Wilson

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11519 ,  H01L27/11565

Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11088088B2

公开(公告)日：2021-08-10

申请号：US16674644

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  John M. Meldrim ,  Lifang Xu

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L27/11524

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

公开(公告)号：US20210151455A1

公开(公告)日：2021-05-20

申请号：US16686830

申请日：2019-11-18

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  John D. Hopkins ,  Roger W. Lindsay ,  Shuangqiang Luo

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L27/11529

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

公开(公告)号：US20210125939A1

公开(公告)日：2021-04-29

申请号：US16662705

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Lifang Xu ,  Jian Li

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.

公开(公告)号：US10923627B2

公开(公告)日：2021-02-16

申请号：US15679958

申请日：2017-08-17

Applicant: Micron Technology, Inc.

Inventor： Scott D. Schellhammer ,  Scott E. Sills ,  Lifang Xu ,  Thomas Gehrke ,  Zaiyuan Ren ,  Anton J. De Villiers

IPC: H01L33/24 ,  H01L33/00 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32

Abstract: Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.

公开(公告)号：US20200176638A1

公开(公告)日：2020-06-04

申请号：US16784879

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Martin F. Schubert ,  Vladimir Odnoblyudov ,  Lifang Xu

IPC: H01L33/38 ,  H01L33/00 ,  H01L33/42 ,  H01L33/40 ,  H01L33/06 ,  H01L33/32 ,  H01L33/50 ,  H01L33/56 ,  H01L33/30

Abstract: Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective.

公开(公告)号：US20200119032A1

公开(公告)日：2020-04-16

申请号：US16160342

申请日：2018-10-15

Applicant: Micron Technology Inc.

Inventor： Yi Hu ,  Jian Li ,  Lifang Xu ,  Xiaosong Zhang

IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: In an example, a method of forming a stacked memory array includes, forming a termination structure passing through a stack of alternating first and second dielectrics in a first region of the stack; forming first and second sets of contacts through the stack of alternating first and second dielectrics in a second region of the stack concurrently with forming the termination structure; forming an opening through the stack of alternating first and second dielectrics between the first and second sets of contacts so that the opening terminates at the termination structure; and removing the first dielectrics from the second region by accessing the first dielectrics through the opening so that the first and second sets of contacts pass through the second dielectrics alternating with spaces corresponding to the removed first dielectrics.

公开(公告)号：US20190206727A1

公开(公告)日：2019-07-04

申请号：US16172218

申请日：2018-10-26

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.