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公开(公告)号：US12058329B2
公开(公告)日：2024-08-06
申请号：US18200069
申请日：2023-05-22
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Yusuke Kato
IPC: H04N19/13 , H04L65/70 , H04L65/75 , H04N19/176 , H04N19/184 , H04N19/70
CPC classification number: H04N19/13 , H04L65/70 , H04L65/75 , H04N19/176 , H04N19/184 , H04N19/70
Abstract: An encoder includes memory and circuitry which: (i) encodes an image block; (ii) when encoding the image block: binarizes coefficient information indicating coefficients of the image block; and controls whether to apply arithmetic encoding to a binary data string obtained by binarizing the coefficient information; and (iii) when binarizing the coefficient information: binarizes the coefficient information according to a first syntax structure when arithmetic encoding is applied to the data string and a predetermined condition is not satisfied; binarizes the coefficient information according to a second syntax structure when arithmetic encoding is applied to the data string and the predetermined condition is satisfied; binarizes the coefficient information according to the second syntax structure when no arithmetic encoding is applied to the data string; and subtracts 1 from a value of an initial non-zero coefficient when no arithmetic encoding is applied to the data string when encoding the image block.
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公开(公告)号：US12022118B2
公开(公告)日：2024-06-25
申请号：US17499292
申请日：2021-10-12
Inventor： Yusuke Kato , Takahiro Nishi , Tadamasa Toma , Kiyofumi Abe
IPC: H04N19/61 , H04N19/103 , H04N19/13 , H04N19/136 , H04N19/176 , H04N19/46 , H04N19/70 , H04N19/91
CPC classification number: H04N19/61 , H04N19/13 , H04N19/176 , H04N19/46 , H04N19/70 , H04N19/91 , H04N19/103 , H04N19/136
Abstract: An encoder includes circuitry and memory. In both of a first type of residual coding where an orthogonal transform is applied to a current block and a second type of residual coding where the orthogonal transform is skipped, wherein when a number of CABAC processes is within an allowable range, the circuitry encodes coefficient information flags by CABAC, each of the coefficient information flags relating to a coefficient included in the current block; and otherwise, the circuitry skips the encoding of the coefficient information flags; and the circuitry encodes a remainder value of the coefficient with Golomb-Rice code when the coefficient information flags are encoded; and the circuitry encodes a value of the coefficient with the Golomb-Rice code when the plurality of coefficient information flags are not encoded, wherein the coefficient information flags are partially different between the first type of residual coding and the second type of residual coding.
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公开(公告)号：US12003778B2
公开(公告)日：2024-06-04
申请号：US17830577
申请日：2022-06-02
Inventor： Virginie Drugeon , Takahiro Nishi , Kiyofumi Abe , Tadamasa Toma , Yusuke Kato
IPC: H04N19/70 , H04N19/172 , H04N19/174
CPC classification number: H04N19/70 , H04N19/172 , H04N19/174
Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry: assigns a picture level slice index and a subpicture level slice index to each of the slices, the picture level slice index being assigned at a picture level, the subpicture level slice index being assigned at a subpicture level; for each of the slices, encodes the subpicture level slice index of the slice into a slice header of the slice; and encodes each of the slices into a bitstream. The picture level slice index assigned to a current slice to be processed that is included in a current subpicture to be processed is calculated by adding (i) the subpicture level slice index of the current slice and (ii) a total number of slices included in one or more subpictures that have been encoded prior to the current subpicture out of the subpictures.
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公开(公告)号：US20240146968A1
公开(公告)日：2024-05-02
申请号：US18410372
申请日：2024-01-11
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/65 , H04N19/109 , H04N19/157 , H04N19/176 , H04N19/51
CPC classification number: H04N19/65 , H04N19/109 , H04N19/157 , H04N19/176 , H04N19/51
Abstract: An encoder that encodes a moving picture using an inter prediction process, and includes circuitry and memory coupled to the circuitry. In the inter prediction process, when performing a correction process which is a local illumination compensation (LIC) process for a prediction image, the circuitry, in operation; performs the correction process on a prediction image generated using a finally-derived motion vector that is finally derived in a stage before the correction process; and after the correction process, determines, as a final prediction image, the prediction image subjected to the correction process, without applying other correction process on the prediction image.
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公开(公告)号：US11971546B2
公开(公告)日：2024-04-30
申请号：US18325906
申请日：2023-05-30
Inventor： Ryuichi Kanoh , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N11/02 , B60K35/00 , F21V8/00 , G02B5/04 , G02B6/00 , G02B19/00 , G02B27/01 , H04N19/124 , H04N19/159 , H04N19/176 , H04N19/18 , H04N19/66 , H04N19/91 , H04N19/96 , G09G3/34
CPC classification number: G02B27/0149 , B60K35/00 , G02B5/045 , G02B6/00 , G02B6/002 , G02B6/0023 , G02B6/0025 , G02B6/003 , G02B6/0048 , G02B6/0068 , G02B19/0028 , G02B19/0061 , G02B27/0101 , H04N19/124 , H04N19/159 , H04N19/176 , H04N19/18 , H04N19/66 , H04N19/91 , H04N19/96 , G02B2027/015 , G02B2027/0154 , G09G3/3426 , G09G2380/10
Abstract: An image encoder performs a first partitioning including using a first partition mode, without writing first splitting information indicative of the first partition mode into a bitstream, to split a first block into a plurality of second blocks in response to that the first block is located adjacent to an edge of a picture and that the dimensions of the first block satisfy a first condition; and performs a second partitioning on the second block by writing second splitting information indicative of a second partition mode into the bitstream, wherein the second partition mode allows at least one of a quad tree splitting and a binary splitting, and using the second partition mode to split the second block into a plurality of coding units (CUs), wherein the second partition mode prohibits the quad tree splitting of the second block in certain conditions.
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Patent Agency Ranking
公开(公告)号：US11968378B2
公开(公告)日：2024-04-23
申请号：US17994591
申请日：2022-11-28
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/196 , H04N19/105 , H04N19/14 , H04N19/176 , H04N19/436
CPC classification number: H04N19/196 , H04N19/105 , H04N19/14 , H04N19/176 , H04N19/436
Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives a correction parameter using only a neighboring reconstructed image that neighbors a processing unit which has a determined size and is located at an upper left of a current block to be processed in an image, among neighboring reconstructed images that neighbor the current block, and performs correction processing of the current block based on the correction parameter derived, when the current block has a size larger than the determined size.
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公开(公告)号：US11959740B2
公开(公告)日：2024-04-16
申请号：US16299564
申请日：2019-03-12
Inventor： Takahiro Nishi , Tadamasa Toma , Toshiyasu Sugio , Toru Matsunobu , Satoshi Yoshikawa , Tatsuya Koyama
CPC classification number: G01B21/04 , G01B11/00 , G01B21/00 , G06T9/001 , G06T9/004 , G08G1/161 , H04L67/04 , H04L67/5651
Abstract: A three-dimensional data creation method for use in a vehicle including a sensor and a data receiver that transmits and receives three-dimensional data to and from an external device. The three-dimensional data creation method includes: creating second three-dimensional data based on information detected by the sensor and first three-dimensional data received by the data receiver; and transmitting, to the external device, third three-dimensional data that is part of the second three-dimensional data.
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公开(公告)号：US11895322B2
公开(公告)日：2024-02-06
申请号：US18056963
申请日：2022-11-18
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh , Chong Soon Lim , Ru Ling Liao , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Jing Ya Li
IPC: H04N11/02 , H04N19/52 , H04N19/119 , H04N19/176
CPC classification number: H04N19/52 , H04N19/119 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
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公开(公告)号：US11889105B2
公开(公告)日：2024-01-30
申请号：US18057440
申请日：2022-11-21
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh , Chong Soon Lim , Ru Ling Liao , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Jing Ya Li
IPC: H04N11/02 , H04N19/52 , H04N19/119 , H04N19/176
CPC classification number: H04N19/52 , H04N19/119 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
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公开(公告)号：US11882283B2
公开(公告)日：2024-01-23
申请号：US18148990
申请日：2022-12-30
Inventor： Sughosh Pavan Shashidhar , Hai Wei Sun , Chong Soon Lim , Ru Ling Liao , Han Boon Teo , Jing Ya Li , Takahiro Nishi , Kiyofumi Abe , Ryuichi Kanoh , Tadamasa Toma
IPC: H04N11/02 , H04N19/119 , H04N19/176 , H04N19/184 , H04N19/60
CPC classification number: H04N19/119 , H04N19/176 , H04N19/184 , H04N19/60
Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; splits the block into a plurality of sub blocks in a second direction parallel to the second shorter side of the block when the ternary split process is not allowed; and encodes the plurality of sub blocks.
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