公开(公告)号：US20230328973A1

公开(公告)日：2023-10-12

申请号：US17716698

申请日：2022-04-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Jiahui Yuan ,  Senaka Kanakamedala

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an etch stop dielectric material sublayer having a material composition that is different from the insulating material. The etch stop dielectric material sublayer can be employed as an etch stop structure during formation of the drain-select-level isolation structure through drain-select-level electrically conductive layers.

公开(公告)号：US11778817B2

公开(公告)日：2023-10-03

申请号：US16912196

申请日：2020-06-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Kumar Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H10B43/27 ,  H01L21/762 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H01L21/02

CPC classification number: H10B43/27 ,  H01L21/76254 ,  H01L24/08 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/02595 ,  H01L21/02598 ,  H01L2224/08145

Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

公开(公告)号：US11659711B2

公开(公告)日：2023-05-23

申请号：US17090420

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki Kasai ,  Shigehisa Inoue ,  Tomohiro Asano ,  Raghuveer S. Makala

IPC: H10B43/27 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures. Insulating layers comprising silicon oxide are formed by oxidizing surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities. Remaining portions of the charge storage material layers form vertical stacks of discrete charge storage elements. Remaining portions of the silicon nitride layers are replaced with electrically conductive layers.

公开(公告)号：US11594490B2

公开(公告)日：2023-02-28

申请号：US17155541

申请日：2021-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a respective conductive liner comprising molybdenum carbide or carbonitride, and a respective molybdenum metal fill material portion.

公开(公告)号：US11569260B2

公开(公告)日：2023-01-31

申请号：US17001003

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Rahul Sharangpani

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11543 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519

Abstract: A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.

公开(公告)号：US11545506B2

公开(公告)日：2023-01-03

申请号：US17097757

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati Prasad ,  Joyeeta Nag ,  Seung-Yeul Yang ,  Adarsh Rajashekhar ,  Raghuveer S. Makala

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/66 ,  H01L29/51 ,  H01L27/1159

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US11538828B2

公开(公告)日：2022-12-27

申请号：US16984920

申请日：2020-08-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L29/417 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556

Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.

公开(公告)号：US11538817B2

公开(公告)日：2022-12-27

申请号：US16913766

申请日：2020-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Johann Alsmeier

IPC: H01L27/11507 ,  H01L27/22 ,  H01L27/24 ,  H01L27/11504 ,  H01L43/02 ,  H01L45/00 ,  H01L43/12 ,  H01L43/08

Abstract: At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

公开(公告)号：US11508748B2

公开(公告)日：2022-11-22

申请号：US16887818

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Peter Rabkin ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/522 ,  H01L27/11543 ,  H01L27/11556 ,  H01L29/207 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US11450687B2

公开(公告)日：2022-09-20

申请号：US17122360

申请日：2020-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Tirukkonda ,  Ramy Nashed Bassely Said ,  Senaka Kanakamedala ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Fei Zhou

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11585 ,  H01L27/11578

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.