公开(公告)号：US07369433B2

公开(公告)日：2008-05-06

申请号：US11476023

申请日：2006-06-28

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C16/04

CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3445 ,  G11C16/3459

摘要： A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first and second cell arrays, one of four data levels L0, L1, L2 and L3 (where, L0

摘要翻译： 半导体存储器件包括：第一和第二单元阵列，每个具有多个存储单元; 以及用于读出第一和第二单元阵列的数据的读出放大器电路，其中在第一和第二单元阵列中的每一个中设置多个信息单元和至少一个参考单元，四个数据电平L 0，L 1， 写入信息单元的L 2和L 3（其中，L 0

公开(公告)号：US20070285967A1

公开(公告)日：2007-12-13

申请号：US11761397

申请日：2007-06-12

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： G11C11/36

CPC分类号： G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array, wherein the variable resistance element comprises a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

摘要翻译： 一种电阻变化存储器件，包括：半导体衬底; 形成在所述半导体衬底上的至少一个单元阵列，每个存储单元具有可变电阻元件和存取元件的堆叠结构，所述存取元件具有在十倍或更多的一定电压范围内的截止电阻值 与选择状态一样高; 以及形成在半导体衬底上的单元阵列下面的读/写电路，其中，所述可变电阻元件包括由A x M y Y y表示的第一复合化合物形成的记录层， 其中“A”和“M”是彼此不同的阳离子元素;“O”氧; 0.5 <= x <= 1.5,0.5 <= y <= 2.5和 1.5 <= z <= 4.5）和包含至少一个过渡元素和用于容纳阳离子离子的空腔部位的第二复合化合物。

公开(公告)号：US07154775B2

公开(公告)日：2006-12-26

申请号：US10614814

申请日：2003-07-09

申请人： Yuui Shimizu ,  Haruki Toda

发明人： Yuui Shimizu ,  Haruki Toda

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： A magnetic random access memory includes a memory cell array in which memory cells, each having a magnetoresistive element as a storage element, are arranged, word lines respectively connected to rows of the memory cell array, bit lines respectively connected to columns of the memory cell array, row decoders to select the word lines, and a column decoder to select the bit lines. To determine the value of storage data, electrical characteristic values based on storage data stored in the plurality of memory cells are detected, reference data is continuously written in the plurality of memory cells, the reference data written in the plurality of memory cells is continuously read out to detect electrical characteristic values based on the reference data, and the electrical characteristic values based on the storage data are compared with those based on the reference data.

摘要翻译： 磁性随机存取存储器包括一个存储单元阵列，其中排列有各自具有磁阻元件作为存储元件的存储单元，分别连接到存储单元阵列的行的字线，分别连接到存储单元的列的位线 阵列，行解码器选择字线，以及列解码器来选择位线。 为了确定存储数据的值，检测基于存储在多个存储单元中的存储数据的电特性值，将参考数据连续写入多个存储单元，写入多个存储单元的参考数据被连续读取 基于参考数据检测电特性值，并将基于存储数据的电特性值与基于参考数据的电特性值进行比较。

公开(公告)号：US20060152979A1

公开(公告)日：2006-07-13

申请号：US11299758

申请日：2005-12-13

申请人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

发明人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC分类号： G11C7/00

CPC分类号： G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

摘要： A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.

公开(公告)号：US07061827B2

公开(公告)日：2006-06-13

申请号：US10688881

申请日：2003-10-21

申请人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

发明人： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC分类号： G11C11/00

CPC分类号： G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

摘要： A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.

摘要翻译： 半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列具有以行和列排列的多个存储单元。 存储单元存储数据，并根据地址信号进行选择。 控制电路被配置为接收时钟信号和第一控制信号，并且在第一控制信号被断言之后响应于时钟信号输出多个数据。 在第一控制信号置位之后，响应时钟信号的内部信号转换N次（N为正整数，大于或等于2），则数据的输出开始。 在输出开始后的转换中输出至少一个数据。

公开(公告)号：US20050111286A1

公开(公告)日：2005-05-26

申请号：US11023397

申请日：2004-12-29

申请人： Haruki Toda ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G11C7/10 ,  G11C8/04 ,  G11C8/00

CPC分类号： G11C8/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2207/2254

摘要： A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

公开(公告)号：US06822917B2

公开(公告)日：2004-11-23

申请号：US10437256

申请日：2003-05-13

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C700

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/229

摘要： There is disclosed a memory system including a memory cell array, a sense amplifier circuit, a write circuit, a level setting circuit, a column decoder, a data line, and a sense amplifier control circuit. The level setting circuit sets external input data to substantially the same level as a read potential difference level from the memory cell. The external input data whose level has been set by the level setting circuit is transferred to the sense amplifier selected by the column decoder via the data line. The sense amplifier control circuit activates the selected sense amplifier so as to write the external input data into the memory cell with substantially the same sequence as that at a data read time from the memory cell.

摘要翻译： 公开了一种包括存储单元阵列，读出放大器电路，写入电路，电平设置电路，列解码器，数据线以及读出放大器控制电路的存储器系统。 电平设置电路将外部输入数据设置为与来自存储单元的读取电位差电平基本相同的电平。 电平已由电平设置电路设置的外部输入数据经由数据线传输到由列解码器选择的读出放大器。 读出放大器控制电路激活所选择的读出放大器，以便以与从存储器单元的数据读取时间基本相同的顺序将外部输入数据写入存储单元。

公开(公告)号：US06715028B1

公开(公告)日：2004-03-30

申请号：US09594925

申请日：2000-06-15

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G06F1200

CPC分类号： G11C7/1051 ,  G11C7/1006

摘要： A selective data memory device includes skip and sequential read circuits that connect input/output lines for inputting and outputting string data, and data set corresponding to the string data, to bit lines. String bit registers temporarily store data on the string data line for inputting selecting string data, and bit comparators compare the string data on the bit lines of the memory cells with data stored in the string bit registers. The string data on the bit lines can be selected by the bit comparators. On the basis of the comparison results, specific data is written in a specific bit position of the bit lines by string match mark circuits. On the basis of the specific bit data, the skip and sequential read circuits can access the memory cells. Therefore, a key string data access is enabled, and it is possible to realize a large capacity memory device for enabling an effective data set access in match with key string data.

摘要翻译： 选择性数据存储装置包括连接用于输入和输出字符串数据的输入/输出线和对应于字符串数据的数据集的跳过和顺序读取电路到位线。 字符串位寄存器临时存储用于输入选择字符串数据的字符串数据线上的数据，并且位比较器将存储器单元的位线上的字符串数据与存储在字符串位寄存器中的数据进行比较。 位线上的字符串数据可以由位比较器选择。 在比较结果的基础上，通过串匹配标记电路将特定数据写入位线的特定位位置。 基于特定比特数据，跳过和顺序读取电路可以访问存储器单元。 因此，能够实现密钥串数据访问，可以实现与密钥串数据匹配的有效数据集访问的大容量存储装置。

公开(公告)号：US06567333B2

公开(公告)日：2003-05-20

申请号：US10173027

申请日：2002-06-18

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C700

CPC分类号： G11C17/18 ,  G11C17/16 ,  G11C29/44

摘要： A fuse circuit comprises first and second electric fuses, a differential amplifier and a switch circuit. The first and second electric fuses have their respective current characteristics changed when a voltage of a predetermined level or more is applied thereto. The differential amplifier receives two voltage signals based on the current characteristics of the first and second electric fuses, outputs a predetermined voltage on the basis of a difference in voltage between the two voltage signals, and amplifies the predetermined voltage. The memory circuit stores an output from the differential amplifier. The switch circuit connects and disconnects the differential amplifier to and from the memory circuit.

公开(公告)号：US06426912B2

公开(公告)日：2002-07-30

申请号：US09887768

申请日：2001-06-21

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C800

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/10 ,  G11C7/18 ,  G11C29/12

摘要： Banks are arranged on a memory chip, forming a matrix. A data input/output circuit is provided at one side of the memory chip. A data bus is provided among the banks and connected to the data input/output circuit. Each bank has a plurality of memory cell arrays a cell-array controller, a row decoder, column decoders, and a DQ buffer. The cell-array controller and the row decoder oppose each other. The column decoders oppose the DQ buffer. Local DQ lines are provided between the memory cell arrays, and global DQ liens extend over the memory cell arrays. The local DQ lines extend at right angles to the global DQ lines.