公开(公告)号：US20210151412A1

公开(公告)日：2021-05-20

申请号：US17140860

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/78 ,  H01L25/00

Abstract: A package and a method of forming the same are provided. A method includes forming a first die structure. The first die structure includes a die stack and a stacked dummy structure bonded to a carrier. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is a farthest integrated circuit die of the die stack from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.

公开(公告)号：US20210125968A1

公开(公告)日：2021-04-29

申请号：US17140547

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/02 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

公开(公告)号：US20210090966A1

公开(公告)日：2021-03-25

申请号：US16877508

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-An Kuo ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

公开(公告)号：US10957610B2

公开(公告)日：2021-03-23

申请号：US16596758

申请日：2019-10-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Chao-Hsiang Yang ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

公开(公告)号：US20210082857A1

公开(公告)日：2021-03-18

申请号：US17106744

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L23/538 ,  H01L25/03 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

公开(公告)号：US20210082779A1

公开(公告)日：2021-03-18

申请号：US16572612

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

IPC: H01L23/10 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

Abstract: Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.

公开(公告)号：US10950576B2

公开(公告)日：2021-03-16

申请号：US16655266

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Hsien-Wei Chen ,  Jiun-Heng Wang ,  Ming-Fa Chen

IPC: H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522

Abstract: A package structure includes a substrate, a first die, a second die and a bonding die. The substrate comprises scribe regions and die regions. The die regions are spaced from each other by the scribe regions therebetween. The first die and the second die are within the die regions of the substrate. The bonding die is electrically bonded to the first die and the second die. The top surfaces of the first die and the second die are partially covered by the bonding die.

公开(公告)号：US20210066222A1

公开(公告)日：2021-03-04

申请号：US16929708

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768

Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.

公开(公告)号：US20210066192A1

公开(公告)日：2021-03-04

申请号：US16929118

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Sen-Bor Jan

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package has a first region and a second region. The package includes a first die, a second die, an encapsulant, and an inductor. The second die is stacked on and bonded to the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. A metal density in the first region is greater than a metal density in the second region.

公开(公告)号：US20210066191A1

公开(公告)日：2021-03-04

申请号：US16876111

申请日：2020-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: Semiconductor packages are provided. One of the semiconductor packages includes an integrated circuit, a die, an encapsulant and an inductor. The die is bonded to the integrated circuit. The encapsulant encapsulates the die over the integrated circuit. The inductor includes a plurality of first conductive patterns and a plurality of second conductive patterns. The first conductive patterns penetrate through the encapsulant. The second conductive patterns are disposed over opposite surfaces of the encapsulant. The first conductive patterns and the second conductive patterns are electrically connected to one another to form a spiral structure having two ends.