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公开(公告)号：US10483174B1
公开(公告)日：2019-11-19
申请号：US16016662
申请日：2018-06-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzuan-Horng Liu , Chao-Hsiang Yang , Hsien-Wei Chen , Ming-Fa Chen
IPC: H01L21/66 , H01L23/00 , H01L23/498 , H01L23/31
Abstract: A package structure includes a semiconductor substrate, conductive pads, and conductive vias. The conductive pads are located on and electrically connected to the semiconductor substrate, and each have a testing region and a contact region comprising a core contact region and a buffer contact region, wherein along one direction, the conductive pads each have a maximum length less than a sum of a maximum length of the testing region and a maximum length of the buffer contact region. The conductive vias are respectively located on the core contact regions of the conductive pads.
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公开(公告)号：US20200264231A1
公开(公告)日：2020-08-20
申请号：US16869775
申请日：2020-05-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.
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公开(公告)号：US10663512B2
公开(公告)日：2020-05-26
申请号：US16232373
申请日：2018-12-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.
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公开(公告)号：US20200043816A1
公开(公告)日：2020-02-06
申请号：US16596758
申请日：2019-10-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzuan-Horng Liu , Chao-Hsiang Yang , Hsien-Wei Chen , Ming-Fa Chen
IPC: H01L21/66 , H01L23/498 , H01L23/31 , H01L23/00
Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
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公开(公告)号：US10957610B2
公开(公告)日：2021-03-23
申请号：US16596758
申请日：2019-10-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzuan-Horng Liu , Chao-Hsiang Yang , Hsien-Wei Chen , Ming-Fa Chen
IPC: H01L21/66 , H01L23/00 , H01L23/498 , H01L23/31
Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
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Patent Agency Ranking
公开(公告)号：US10175294B2
公开(公告)日：2019-01-08
申请号：US15481891
申请日：2017-04-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.
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公开(公告)号：US11169207B2
公开(公告)日：2021-11-09
申请号：US16869775
申请日：2020-05-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.
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公开(公告)号：US20170212167A1
公开(公告)日：2017-07-27
申请号：US15481891
申请日：2017-04-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
CPC classification number: G01R31/2896 , G01R1/0416 , G01R31/2601 , G01R31/2884 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02377 , H01L2224/0392 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05552 , H01L2224/05568 , H01L2224/05655 , H01L2224/0614 , H01L2224/0616 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13083 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16238 , H01L2924/20752 , H01L2924/00012 , H01L2924/00014 , H01L2924/01047 , H01L2924/014
Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.
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公开(公告)号：US09618572B2
公开(公告)日：2017-04-11
申请号：US15170062
申请日：2016-06-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
CPC classification number: G01R31/2896 , G01R1/0416 , G01R31/2601 , G01R31/2884 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02377 , H01L2224/0392 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05552 , H01L2224/05568 , H01L2224/05655 , H01L2224/0614 , H01L2224/0616 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13083 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16238 , H01L2924/20752 , H01L2924/00012 , H01L2924/00014 , H01L2924/01047 , H01L2924/014
Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.
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公开(公告)号：US20190128958A1
公开(公告)日：2019-05-02
申请号：US16232373
申请日：2018-12-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
CPC classification number: G01R31/2896 , G01R1/0416 , G01R31/2601 , G01R31/2884 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02377 , H01L2224/0392 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05552 , H01L2224/05568 , H01L2224/05655 , H01L2224/0614 , H01L2224/0616 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13083 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16238 , H01L2924/20752 , H01L2924/00012 , H01L2924/00014 , H01L2924/01047 , H01L2924/014
Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.
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