中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

339 records (took 0.036 seconds)

    THREE-DIMENSIONAL MEMORY DEVICE WITH FERROELECTRIC MATERIAL
    131.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH FERROELECTRIC MATERIAL 有权

    公开(公告)号：US20210375929A1

    公开(公告)日：2021-12-02

    申请号：US17070536

    申请日：2020-10-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

    IPC: H01L27/11597 ,  H01L27/11587

    Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

    Semiconductor Devices with Embedded Ferroelectric Field Effect Transistors
    133.
    发明申请
    Semiconductor Devices with Embedded Ferroelectric Field Effect Transistors 有权

    公开(公告)号：US20210273113A1

    公开(公告)日：2021-09-02

    申请号：US16939909

    申请日：2020-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Han-Jong Chia ,  Bo-Feng Young ,  Yu-Ming Lin

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51

    Abstract: A method includes providing a structure having a substrate, gate stacks and source/drain (S/D) features over the substrate, S/D contacts over the S/D features, one or more dielectric layers over the gate stacks and the S/D contacts, and a via structure penetrating the one or more dielectric layers and electrically connecting to one of the gate stacks and the S/D contacts. The method further includes forming a ferroelectric (FE) stack over the structure, wherein the FE stack includes an FE layer and a top electrode layer over the FE layer, wherein the FE stack directly contacts the via structure; and patterning the FE stack, resulting in a patterned FE stack including a patterned FE feature and a patterned top electrode over the patterned FE feature.

    Low parasitic resistance contact structure
    136.
    发明授权
    Low parasitic resistance contact structure 有权

    公开(公告)号：US11043594B2

    公开(公告)日：2021-06-22

    申请号：US16441107

    申请日：2019-06-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

    Methods of Forming Source/Drain Contacts in Field-Effect Transistors
    140.
    发明申请
    Methods of Forming Source/Drain Contacts in Field-Effect Transistors 审中-公开

    公开(公告)号：US20200058744A1

    公开(公告)日：2020-02-20

    申请号：US16386853

    申请日：2019-04-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Tsung Wang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/40 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3105

    Abstract: A method includes forming a first dummy source/drain (S/D) contact over a first epitaxial S/D feature and a second dummy S/D contact over a second epitaxial S/D feature, where first and the second dummy S/D contacts may be formed in an interlayer dielectric (ILD) layer; removing a portion of the first dummy S/D contact, a portion of the second dummy S/D contact, and a portion of the ILD layer disposed between the first and the second dummy S/D contacts to form a first trench; removing a remaining portion of the first dummy S/D contact to form a second trench; and forming a metal S/D contact in the first and the second trenches. The first and the second dummy S/D contacts include a dielectric material different from a dielectric material of the ILD layer.

Patent Agency Ranking