公开(公告)号：US20230200257A1

公开(公告)日：2023-06-22

申请号：US18110337

申请日：2023-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

公开(公告)号：US20230101233A1

公开(公告)日：2023-03-30

申请号：US18074533

申请日：2022-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

公开(公告)号：US20230050435A1

公开(公告)日：2023-02-16

申请号：US17973557

申请日：2022-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Ju-Chun Fan ,  Hung-Yueh Chen

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L45/00 ,  H01L43/12 ,  H01L43/08

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

公开(公告)号：US11552241B2

公开(公告)日：2023-01-10

申请号：US15930425

申请日：2020-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

公开(公告)号：US20220085283A1

公开(公告)日：2022-03-17

申请号：US17533003

申请日：2021-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

公开(公告)号：US20210390993A1

公开(公告)日：2021-12-16

申请号：US17460348

申请日：2021-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

公开(公告)号：US20210226119A1

公开(公告)日：2021-07-22

申请号：US17223025

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L27/22

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

公开(公告)号：US11063207B2

公开(公告)日：2021-07-13

申请号：US16589157

申请日：2019-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.

公开(公告)号：US11018184B2

公开(公告)日：2021-05-25

申请号：US16532492

申请日：2019-08-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Ying-Cheng Liu ,  Yi-Hui Lee ,  Chin-Yang Hsieh ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01F41/34 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.

公开(公告)号：US11011210B2

公开(公告)日：2021-05-18

申请号：US16592734

申请日：2019-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

IPC: G11C5/06 ,  H01L27/24 ,  H01L27/22

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.