公开(公告)号：US10170362B2

公开(公告)日：2019-01-01

申请号：US15472295

申请日：2017-03-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L23/535 ,  H01L29/06 ,  H01L23/528 ,  H01L27/108

Abstract: The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.

公开(公告)号：US20180342613A1

公开(公告)日：2018-11-29

申请号：US15942568

申请日：2018-04-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L29/78 ,  H01L21/4757 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/7825 ,  H01L21/0229 ,  H01L21/47573 ,  H01L21/76224 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/1057

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and at least a gate trench extending along a first direction formed in the substrate. A gate dielectric layer is formed conformally covering the gate trench. A gate metal is formed on the gate dielectric layer and filling the gate trench. A plurality of intervening structures are arranged along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer.

公开(公告)号：US20180337184A1

公开(公告)日：2018-11-22

申请号：US15629768

申请日：2017-06-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L23/535

CPC classification number: H01L27/10814 ,  H01L23/535 ,  H01L27/10855

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.

公开(公告)号：US20180277354A1

公开(公告)日：2018-09-27

申请号：US15497182

申请日：2017-04-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L21/02 ,  C25F3/12

CPC classification number: C25F3/12 ,  H01L21/31116 ,  H01L23/5258 ,  H01L24/00

Abstract: A method of forming a semiconductor structure is disclosed. A substrate is provided with a pad metal and a fuse metal formed thereon. A liner and an etching stop layer are formed at least covering a top surface of the fuse metal. A dielectric layer is formed on the substrate and a passivation layer is formed over the dielectric layer. A pad opening and a fuse opening are defined in the passivation layer. A first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening to expose a top surface of the pad metal from the pad opening and an upper surface of the etching stop layer from the fuse opening respectively. A second etching step is performed to remove the etching stop layer from the fuse opening until an upper surface of the liner is exposed.

公开(公告)号：US10043809B1

公开(公告)日：2018-08-07

申请号：US15632394

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Ching Chang ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.

公开(公告)号：US20180211867A1

公开(公告)日：2018-07-26

申请号：US15866469

申请日：2018-01-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsin-Yu Chiang ,  Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76808 ,  H01L21/31116 ,  H01L21/31138

Abstract: A method for manufacturing dual damascene structures is provided with the steps of forming a via hole through a dielectric layer, forming a sacrificial layer on the dielectric layer filling up the via hole, performing an etch process through a photoresist to form a trench in the dielectric layer, wherein in the etch process the ratio of etching selectivity between the dielectric layer and the sacrificial layer is 1:1, and the trench and the via hole forms collectively a dual damascene recess.

公开(公告)号：US20180190603A1

公开(公告)日：2018-07-05

申请号：US15854785

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chin-Hsin Chiu

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/525 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76895 ,  H01L22/22 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/5256 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/03019 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05019 ,  H01L2224/05083 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48463

Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.

公开(公告)号：US20180108563A1

公开(公告)日：2018-04-19

申请号：US15384940

申请日：2016-12-20

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Hsien-Shih Chu ,  Ming-Feng Kuo ,  Fu-Che Lee ,  Chien-Ting Ho ,  Chiung-Lin Hsu ,  Feng-Yi Chang ,  Yi-Wang Zhan ,  Li-Chiang Chen ,  Chien-Cheng Tsai ,  Chin-Hsin Chiu

IPC: H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/762

Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.

公开(公告)号：US09887088B1

公开(公告)日：2018-02-06

申请号：US15452743

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Ming-Feng Kuo ,  Li-Chiang Chen

IPC: H01L21/28 ,  H01L21/3213

CPC classification number: H01L21/28088 ,  H01L21/32135

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; forming a barrier layer in the trench; forming a conductive layer on the barrier layer; performing a first etching process to remove part of the conductive layer; and performing a second etching process to remove part of the barrier layer. Preferably, the second etching process comprises a non-plasma etching process.

公开(公告)号：US11943909B2

公开(公告)日：2024-03-26

申请号：US17089734

申请日：2020-11-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/311 ,  H01L49/02 ,  H10B12/00

CPC classification number: H10B12/0335 ,  H01L21/311 ,  H01L28/40 ,  H01L28/90 ,  H01L28/92 ,  H10B12/03 ,  H10B12/033 ,  H10B12/31

Abstract: A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.