公开(公告)号：US20240193413A1

公开(公告)日：2024-06-13

申请号：US18065393

申请日：2022-12-13

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ian Charles Colbert ,  Mehdi Saeedi ,  Arun Coimbatore Ramachandran ,  Chandra Kumar Ramasamy ,  Gabor Sines ,  Prakash Sathyanath Raghavendra ,  Alessandro Pappalardo

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: An apparatus and method for efficiently creating less computationally intensive nodes for a neural network. In various implementations, a computing system includes a memory that stores multiple input data values for training a neural network, and a processor. Rather than determine a bit width P of an integer accumulator of a node of the neural network based on bit widths of the input data values and corresponding weight values, the processor selects the bit width P during training. The processor adjusts the magnitudes of the weight values during iterative stages of training the node such that an L1 norm value of the weight values of the node does not exceed a corresponding weight magnitude limit.

公开(公告)号：US20240193292A1

公开(公告)日：2024-06-13

申请号：US18212858

申请日：2023-06-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. Kotra ,  David Kaplan ,  Kishore Punniyamurthy ,  Alexander Toufic Freij

IPC: G06F21/62

CPC classification number: G06F21/6218 ,  G06F2221/2113 ,  G06F2221/2141

Abstract: A processing system receives graph object data and graph object metadata. The processing system stores the graph object metadata inline with the graph object data. The graph object metadata indicates access permissions for corresponding graph objects. Because the graph object metadata is stored inline with the graph object data, the graph object metadata is more easily retrieved and fewer system resources are consumed to determine access permissions of a requester as compared to a system where graph object metadata is stored separately from the graph object data.

公开(公告)号：US20240192994A1

公开(公告)日：2024-06-13

申请号：US18127395

申请日：2023-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad Ashkar ,  Michael Mantor ,  Rex Eldon McCrary ,  Yi Luo ,  Manu Rastogi ,  James Robert Klobcar

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5027 ,  G06F9/4881

Abstract: Techniques for implementing accelerated draw indirect fetching are disclosed. A fetch accelerator enables streamlined data fetching by looping internally and filling a draw queue for a micro engine. By using a dedicated fetch accelerator rather than processing data fetches separately and individually using a conventional processor, significant processing overhead is eliminated and computational latency is reduced. Additionally, different types of aligned or unaligned data structures are usable with equivalent or nearly equivalent performance.

公开(公告)号：US20240192759A1

公开(公告)日：2024-06-13

申请号：US18065313

申请日：2022-12-13

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Stephen Kushnir ,  Sriram Sundaram ,  Christopher Allan Poirier

IPC: G06F1/3296 ,  G06F1/3228 ,  H01L25/065

CPC classification number: G06F1/3296 ,  G06F1/3228 ,  H01L25/0652

Abstract: An apparatus and method for efficiently managing performance among replicated modules of an integrated circuit despite manufacturing variations across semiconductor dies. An integrated circuit includes a first module with a first partition of multiple dies that share at least a same first power rail. The integrated circuit also includes a second module with a second partition of multiple dies that share at least a same second power rail different from the first power rail. The dies within partitions have differences in circuit parameters within a threshold such that the dies can be placed in a same first bin. The dies in different partitions belong to different bins. A power manager initially assigns the same operating parameters to the first partition and the second partition, but adjusts the operating parameters based on detection of the different circuit behavior due to manufacturing variations between the first partition and the second partition.

公开(公告)号：US12002541B2

公开(公告)日：2024-06-04

申请号：US17854924

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Aaron John Nygren ,  Michael John Litt ,  Karthik Gopalakrishnan ,  Tsun Ho Liu

IPC: G11C11/4076 ,  G06F1/08 ,  G06F1/10 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1063 ,  G11C7/1069 ,  G06F1/08 ,  G06F1/10 ,  G11C11/4076

Abstract: A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.

公开(公告)号：US20240168658A1

公开(公告)日：2024-05-23

申请号：US18057539

申请日：2022-11-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Raul Gutierrez

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679

Abstract: Systems, apparatuses, and methods for moving data from a memory in a computing system to an I/O device. A system includes a processor, memory, I/O controller, and power management circuitry. An application stores data in the memory that is to be ultimately conveyed to an I/O device. The I/O controller is configured to convey the data to an I/O device according to a service interval. The I/O controller is configured to fetch a first data item from the memory stored by the application, and prefetch one or more additional data items from memory. The first data and prefetched data are stored in a locally accessible buffer of the I/O controller. The I/O controller is then configured to convey each of the first data and one or more data items from the buffer to the I/O device at regular intervals of time during a given period of time, prior to initiating a fetch of additional data from the memory. During the given period of time, the power management circuitry is configured to cause at least the memory to enter a reduced power state.

公开(公告)号：US20240160743A1

公开(公告)日：2024-05-16

申请号：US18055356

申请日：2022-11-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Nimit Madhubhai Patel

IPC: G06F21/57

CPC classification number: G06F21/575 ,  G06F21/572 ,  G06F2221/033

Abstract: An apparatus and method for providing access to reliable boot firmware. In various implementations, a computing system includes an integrated circuit with a security processor. Prior to performing any steps of a bootup operation using one of multiple copies of boot firmware, the security processor determines whether multiple signatures exist where the signatures are based on the multiple copies of boot firmware. Each of the multiple copies of boot firmware is a copy of a particular version of boot firmware. If the multiple signatures do not yet exist, then the security processor generates the signatures using the multiple copies of boot firmware. During a bootup operation, when the security processor determines that the multiple signatures already exist, the security processor uses these signatures to validate one or more of the multiple copies of boot firmware. The security processor continues with the bootup operation using the validated copy of boot firmware.

公开(公告)号：US11977757B2

公开(公告)日：2024-05-07

申请号：US17732718

申请日：2022-04-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Grant Evan Ley ,  Jayesh Hari Joshi ,  Amitabh Mehra ,  Jerry Anton Ahrens ,  Joshua Taylor Knight ,  Anil Harwani ,  William Robert Alverson

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0673

Abstract: Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of the first memory profile or the second memory profile comprises an overclocking memory profile that configures the memory to operate in an overclocking mode. In one or more implementations, the memory is trained to operate according to the overclocking memory profile prior to operating the memory according to the first memory profile.

公开(公告)号：US20240145565A1

公开(公告)日：2024-05-02

申请号：US17974643

申请日：2022-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard Schultz

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/1025

Abstract: The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adjacent to the oxide layer. The second transistor can include a second channel that is oriented in a direction orthogonal to the first direction, and the first channel and the second channel can be laterally offset such that the second channel does not cross over the first channel. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US20240144581A1

公开(公告)日：2024-05-02

申请号：US17976681

申请日：2022-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Ali Arda Eker

IPC: G06T15/06 ,  G06F7/24 ,  G06T15/08 ,  G06T17/10

CPC classification number: G06T15/06 ,  G06F7/24 ,  G06T15/08 ,  G06T17/10 ,  G06T2210/12

Abstract: A technique for performing ray tracing operations is provided. The technique includes determining a set of keys and a set of values corresponding to dimensions of a bounding box for a scene; sorting the set of keys and the set of values to generate a sorted set of values; and based on the sorted set of values, generating a Morton code for a triangle of the scene.