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    Semiconductor chip with stacked conductor lines and air gaps
    4.
    发明授权
    Semiconductor chip with stacked conductor lines and air gaps 有权

    公开(公告)号：US11004791B2

    公开(公告)日：2021-05-11

    申请号：US16382774

    申请日：2019-04-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Richard Schultz

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.

    ZERO DIFFUSION BREAK BETWEEN STANDARD CELLS USING THREE-DIMENSIONAL CROSS FIELD EFFECT SELF-ALIGNED TRANSISTORS
    6.
    发明申请
    ZERO DIFFUSION BREAK BETWEEN STANDARD CELLS USING THREE-DIMENSIONAL CROSS FIELD EFFECT SELF-ALIGNED TRANSISTORS 有权

    公开(公告)号：US20240403529A1

    公开(公告)日：2024-12-05

    申请号：US18326835

    申请日：2023-05-31

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Richard Schultz ,  Omid Rowhani

    IPC: G06F30/392 ,  G06F30/394 ,  H01L27/118

    Abstract: An apparatus and method for efficiently creating layout of standard cells to improve floor planning of a chip. In various implementations, an integrated circuit uses multiple standard cells with an absence of diffusion breaks at cell boundaries. The standard cells use vertically stacked non-planer transistors. Multiple transistors are formed with an active region having a length between a source region and a drain region of a single transistor. Therefore, the active regions of these transistors are not formed across multiple gate terminals. By having active regions of these transistors formed across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between two active regions of the two adjoining standard cells. This is true even when the two adjoining standard cells share a source/drain region at the cell boundaries. Accordingly, forming diffusion breaks at the edges of these standard cells can be skipped.

    APPARATUSES AND SYSTEMS FOR OFFSET CROSS FIELD-EFFECT TRANSISTORS
    7.
    发明公开
    APPARATUSES AND SYSTEMS FOR OFFSET CROSS FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20240145565A1

    公开(公告)日：2024-05-02

    申请号：US17974643

    申请日：2022-10-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard Schultz

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/1025

    Abstract: The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adjacent to the oxide layer. The second transistor can include a second channel that is oriented in a direction orthogonal to the first direction, and the first channel and the second channel can be laterally offset such that the second channel does not cross over the first channel. Various other apparatuses, systems, and methods are also disclosed.

    SEMICONDUCTOR CHIP WITH STACKED CONDUCTOR LINES AND AIR GAPS
    10.
    发明申请
    SEMICONDUCTOR CHIP WITH STACKED CONDUCTOR LINES AND AIR GAPS 审中-公开

    公开(公告)号：US20200328155A1

    公开(公告)日：2020-10-15

    申请号：US16382774

    申请日：2019-04-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Richard Schultz

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.

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