公开(公告)号：US6144253A

公开(公告)日：2000-11-07

申请号：US949149

申请日：1997-10-27

申请人： Joseph C. Nemer

发明人： Joseph C. Nemer

IPC分类号： H04L27/152 ,  H04L27/14

CPC分类号： H04L27/152

摘要： A FSK demodulator which uses the combination of a digital phase comparator and a digital controlled oscillator (DCO) in the form of a state machine to demodulate an FSK signal. The phase comparator compares the phase of the FSK signal with the output of the DCO to provide a signal to the DCO having a level dependent on the phase relationship between the two signals at the input to the comparator. The demodulator also includes a filter to obtain the data from the signal at the output of the comparator.

摘要翻译： FSK解调器，其以状态机的形式使用数字相位比较器和数字控制振荡器（DCO）的组合来解调FSK信号。 相位比较器将FSK信号的相位与DCO的输出进行比较，以向DCO提供信号，该信号具有取决于比较器输入端的两个信号之间的相位关系的电平。 该解调器还包括一个滤波器，用于从比较器输出端的信号中获得数据。

公开(公告)号：US6072992A

公开(公告)日：2000-06-06

申请号：US894762

申请日：1998-07-17

申请人： Akira Mishima ,  Shigeharu Sumi ,  Motoyoshi Kitagawa

发明人： Akira Mishima ,  Shigeharu Sumi ,  Motoyoshi Kitagawa

IPC分类号： H01F21/02 ,  H01F21/04 ,  H01F41/04 ,  H03B5/18 ,  H03J1/00 ,  H03J1/14 ,  H03J3/00 ,  H03J7/06 ,  H03L7/099 ,  H03L7/18 ,  H04L27/152 ,  H04L27/227 ,  H04L27/233 ,  H03J3/28 ,  H03J5/02 ,  H03L7/08 ,  H04L27/22

CPC分类号： H03L7/0805 ,  H01F21/02 ,  H01F21/04 ,  H01F41/045 ,  H03B5/1841 ,  H03J1/0041 ,  H03J1/005 ,  H03J1/14 ,  H03J3/00 ,  H03J7/065 ,  H03L7/099 ,  H03L7/18 ,  H04L27/152 ,  H04L27/227 ,  H04L27/233

摘要： A high frequency apparatus for receiving digital modulated high frequency signal which withstands vibration and is easy to adjust for tuning, yet presents clear oscillation signal. The invented apparatus has an input terminal(101), a mixer(104) which receives at one input the signals supplied to input terminal(101) and at the other input an output signal of local oscillator(103), and output terminals(107,108) to which the output signal of mixer(104) is delivered. A voltage controlled oscillator constituting said local oscillator(103) has an oscillating section and a tuning section; the tuning section has a movable conductive member(119) and a gluing agent(120) for maintaining a state after adjustment. Control loop has a high loop band width which is large enough so as the noise of local oscillator(103) is not dominated by noise of the above mentioned voltage controlled oscillator.

摘要翻译： PCT No.PCT / JP95 / 02668 Sec。 371日期：1998年7月17日 102（e）日期1998年7月17日PCT 1995年12月25日PCT公布。 第WO97 / 23953号公报 日期1997年7月3日用于接收数字调制高频信号的高频装置，其承受振动并且易于调节以调谐，但呈现清晰的振荡信号。 本发明的装置具有输入端（101），混频器（104），其在一个输入端接收提供给输入端（101）的信号，另一端接收本地振荡器（103）的输出信号，输出端（107,108 ），输送混频器（104）的输出信号。 构成所述本地振荡器（103）的压控振荡器具有振荡部分和调谐部分; 调谐部分具有用于在调节之后维持状态的可移动导电部件（119）和胶粘剂（120）。 控制回路具有足够大的环路带宽，使得本地振荡器（103）的噪声不受上述压控振荡器的噪声的支配。

公开(公告)号：US6040738A

公开(公告)日：2000-03-21

申请号：US201176

申请日：1998-11-30

申请人： Jun Uchida

发明人： Jun Uchida

IPC分类号： H04L27/38 ,  H03D7/16 ,  H04B1/16 ,  H04B1/26 ,  H04B1/30 ,  H04B15/00 ,  H04L27/00 ,  H04L27/14 ,  H04L27/227 ,  H04Q7/14 ,  H03D3/00 ,  H04L27/152 ,  H04Q7/18

CPC分类号： H03D7/165 ,  H04L27/0014 ,  H04L2027/0028 ,  H04L2027/0057

摘要： A direct conversion receiver includes a reference clock signal generating section for generating reference clock signal. An amplifier section amplifies a received signal and extracts a desired signal from the amplified signal. An extraction reference clock signal generating section frequency-divides the reference clock signal based on a frequency division data to generate first and second extraction reference clock signals. An extracting section extracts a data from the desired signal and the first and second extraction reference clock signals. A control and processing section outputs the frequency division data to the extraction reference clock signal generating section and processes the data based on a control section clock signal corresponding to the reference clock signal.

摘要翻译： 直接转换接收器包括用于产生参考时钟信号的参考时钟信号产生部分。 放大器部分放大接收的信号并从放大的信号中提取期望的信号。 提取参考时钟信号产生部分基于分频数据对参考时钟信号进行分频，以产生第一和第二提取参考时钟信号。 提取部分从期望信号和第一和第二提取参考时钟信号中提取数据。 控制和处理部分将分频数据输出到提取基准时钟信号产生部分，并且基于与参考时钟信号相对应的控制部分时钟信号处理该数据。

公开(公告)号：US6038268A

公开(公告)日：2000-03-14

申请号：US802161

申请日：1997-02-14

申请人： Kazuo Kawai

发明人： Kazuo Kawai

IPC分类号： H04L27/14 ,  H04B1/30 ,  H04L27/152

CPC分类号： H04L27/1525

摘要： In this disclosure, a single combination of a multiplier and amplifier is utilized in a time-sharing manner for two-axis, in-phase an orthogonal phase components (I-axis and Q-axis components, respectively) so that the problem of a phase error relating to the use of the two separate circuits which are used for the respective two-axis components cannot be produced. Further, in this disclosure, this amplifier is constructed as a variable gain amplifier for the purpose of the application of AGC (automatic gain control) through the use of signal power obtained form the amplifier output, and any DC offset is automatically corrected using detecting and correcting means. After a process has been made in which the two-axis components are separated from the amplifier output, frequency detection is made by a frequency detector with linear frequency detection characteristics, which carries out a calculating operation of the separated two-axis components, and an output signal is provided by two-value judging the demodulated output thus obtained. Further, by carrying out comparison between the input and output of the two-value judging circuit, any center frequency error of the FSK signal is detected irrespective of code contents of the FSK signal, and the frequency of the local carrier for the direct conversion is controlled using the thus detected frequency error output.

摘要翻译： 在本公开中，乘法器和放大器的单一组合以两轴同相正交相位分量（分别为I轴和Q轴分量）的时间共享方式被利用，使得 不能产生与用于各个两轴部件的两个分离电路的使用有关的相位误差。 此外，在本公开中，该放大器被构造为可变增益放大器，用于通过使用从放大器输出获得的信号功率来应用AGC（自动增益控制），并且任何DC偏移通过检测和 修正手段。 在将两轴分量与放大器输出分离的处理之后，通过频率检测器进行频率检测，该频率检测器具有线性频率检测特性，其执行分离的两轴分量的计算操作，以及 输出信号由两值判断由此得到的解调输出。 此外，通过进行两值判定电路的输入和输出之间的比较，检测FSK信号的任何中心频率误差，而与FSK信号的代码内容无关，并且用于直接转换的本地载波的频率为 使用这样检测的频率误差输出进行控制。

公开(公告)号：US5994953A

公开(公告)日：1999-11-30

申请号：US049870

申请日：1998-03-27

申请人： David Burshtein ,  Doron Rainish

发明人： David Burshtein ,  Doron Rainish

IPC分类号： H04L25/49 ,  H04L27/152 ,  H04L27/14

CPC分类号： H04L25/4904 ,  H04L27/1525

摘要： A symbol detector for frequency modulated (FM) symbols includes a section determiner, a direction of movement determiner and a data symbol determiner. The section determiner receives a sample of in-phase and quadrature signals associated with a baseband transmitted FM symbol and determines the section value of a unit circle in an in-phase--quadrature coordinate system in which the sample lies. The direction of movement determiner receives the section value of a current sample and the section value of a neighboring sample and generates a positive direction of movement value if the direction of movement along the unit circle from the neighboring sample to the current sample is counterclockwise, a negative direction of movement value if the direction of movement is clockwise and 0 otherwise. The data symbol determiner receives the direction of movement values and decodes the transmitted FM symbol by masking N direction of movement values.

摘要翻译： 用于频率调制（FM）符号的符号检测器包括部分确定器，移动确定器的方向和数据符号确定器。 部分确定器接收与基带传输的FM符号相关联的同相和正交信号的样本，并确定样本所在的同相正交坐标系中的单位圆的截面值。 移动确定器的方向接收当前采样的截面值和相邻采样的截面值，并且如果沿着从相邻采样到当前采样的单位圆的移动方向是逆时针方向，则生成正的运动方向值，a 如果运动方向为顺时针方向，则为负方向运动值，否则为0。 数据符号确定器接收移动值的方向，并通过屏蔽移动值的N个方向对发送的FM符号进行解码。

公开(公告)号：US5960040A

公开(公告)日：1999-09-28

申请号：US761103

申请日：1996-12-05

申请人： Khiem V. Cai ,  Allan L. Levine, Jr.

发明人： Khiem V. Cai ,  Allan L. Levine, Jr.

IPC分类号： H04L27/10 ,  H03M13/23 ,  H04L1/00 ,  H04L27/00 ,  H04L27/12 ,  H04L27/152 ,  H04L27/18 ,  H04L27/20 ,  H04L27/233 ,  H04L27/32

CPC分类号： H04L27/1525 ,  H04L1/0054 ,  H04L27/0008 ,  H04L27/2332 ,  H04L2027/0067

摘要： A digital signal processor is provided which is compatible with a large variety of modulation processes (e.g., BPSK, QPSK,.pi./4 QPSK, M-ary FSK and M-ary PSK). The processor has a transmit section which can convert input data streams into baseband I and Q signals and a receive section which can recover data streams from input baseband I and Q signals. The transmit section includes a direct I/Q modulator and a common phase modulator and the receive section includes an M-FSK to M-PSK converter and a common phase demodulator. The processor is particularly suited for realization as an application-specific integrated circuit (ASIC) which can be integrated in multiband, multimode transceivers.

摘要翻译： 提供一种数字信号处理器，其与各种调制过程（例如，BPSK，QPSK，pi / 4QPSK，M-ary FSK和M-ary PSK）兼容。 处理器具有可将输入数据流转换为基带I和Q信号的发送部分以及可从输入基带I和Q信号恢复数据流的接收部分。 发送部分包括直接I / Q调制器和公共相位调制器，接收部分包括M-FSK至M-PSK转换器和公共相位解调器。 该处理器特别适合作为专用集成电路（ASIC）的实现，该集成电路可集成在多频带多模收发器中。

公开(公告)号：US5422911A

公开(公告)日：1995-06-06

申请号：US121857

申请日：1993-09-17

申请人： Raymond L. Barrett, Jr. ,  Barry W. Herold

发明人： Raymond L. Barrett, Jr. ,  Barry W. Herold

IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/183 ,  H04L27/152

CPC分类号： H03L7/183 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/107 ,  H03L2207/04 ,  H03L2207/06

摘要： A selective call receiver (100) includes a phase lock loop frequency synthesizer having a programmable output frequency signal (414) responsive to a control current signal (417). The phase lock loop frequency synthesizer includes a programmable gain current multiplier (412), a gain of which is determined by a control word selected such that a loop gain of the synthesizer remains relatively constant over a predetermined operating domain of a programmable output frequency signal (417). The current multiplier generates (412) the control current signal (417) by subtracting a reference current (415) from a limited current (416), thus bounding a range of the control current signal (417) within a maximum value of substantially the reference current (415) and a minimum value of the difference between the reference current (415) and the limited current (416).

摘要翻译： 选择呼叫接收机（100）包括具有响应于控制电流信号（417）的可编程输出频率信号（414）的锁相环频率合成器。 锁相环频率合成器包括可编程增益电流乘法器（412），其增益由所选择的控制字确定，使得合成器的环路增益在可编程输出频率信号的预定操作域上保持相对恒定（ 417）。 电流乘法器通过从受限电流（416）减去参考电流（415）来产生（412）控制电流信号（417），从而将控制电流信号（417）的范围限定在基本上为参考的最大值内 电流（415）和参考电流（415）与受限电流（416）之间的差的最小值。

公开(公告)号：US5420888A

公开(公告)日：1995-05-30

申请号：US886676

申请日：1992-05-21

申请人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi

发明人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi

IPC分类号： H04L27/152 ,  H04L27/14

CPC分类号： H04L27/1525

摘要： A system and method for efficient operation of a digital signal processor allows execution of a noncoherent FSK demodulation process at the baud rate of the incoming signal. First and second signal detecting channels terminate at a summing junction. A signal sampler for applying a sampled signal to the first and second signal detecting channels. The first and second signal detecting channels each include, in series, a finite impulse response filter for filtering out energy outside a selected bandwidth, automatic gain control and a demodulator. The finite impulse response filter means for the second signal detecting channel further shifts the phase of the sampled signal in the second signal detecting channel approximately 90 degrees relative to the sampled signal in the first signal detecting channel. The demodulator in each signal detecting channel further includes first and second sampled signal transmission paths terminating in a multiplying junction. The first signal transmission path in each demodulator includes a tunable delay line. The decoder takes its input from the summing junction for reproducing a signal indicating presence of a particular frequency or reproduction of the baseband signal.

摘要翻译： 用于数字信号处理器的有效操作的系统和方法允许以输入信号的波特率执行非相干FSK解调过程。 第一和第二信号检测通道终止于加法结。 一种用于将采样信号施加到第一和第二信号检测通道的信号采样器。 第一和第二信号检测通道各自包括用于滤出选定带宽以外的能量的有限脉冲响应滤波器，自动增益控制和解调器。 用于第二信号检测通道的有限脉冲响应滤波器装置进一步使第二信号检测通道中的采样信号的相位相对于第一信号检测通道中的采样信号大约90度。 每个信号检测信道中的解调器还包括终止于乘法结的第一和第二采样信号传输路径。 每个解调器中的第一信号传输路径包括可调延迟线。 解码器从加法结接收其输入，以再现指示特定频率的存在或基带信号的再现的信号。

公开(公告)号：US5402446A

公开(公告)日：1995-03-28

申请号：US119676

申请日：1993-09-13

申请人： Yoichiro Minami

发明人： Yoichiro Minami

IPC分类号： H04B1/26 ,  H04L7/00 ,  H04L27/14 ,  H04L27/152 ,  H04L27/06

CPC分类号： H04L27/152

摘要： In an FSK receiver of double superheterodyne type for receiving an FSK modulated wave and comprising a PLL local oscillator (10) for ensuring a phase-locked loop to produce a first local oscillation signal and a demodulating section (12) for demodulating the FSK modulated wave into a demodulated signal using the first local oscillation signal and a second local oscillation signal, a control signal producing circuit (14) produces a control signal when the demodulated signal has a mean value indicative of a deviation from a phase lock in the phase-locked loop. Connected to the demodulating section, a synchronizing circuit (16) establishes bit and frame synchronization on the basis of a binary digital signal obtained by deciding the demodulated signal to produce a synchronization detection signal when the bit and frame synchronization is established. Connected to the PLL local oscillator, the control signal producing circuit, and the synchronizing circuit, an intermittent driving circuit (18) makes the PLL local oscillator intermittently operate on the basis of the control signal and the synchronization detection signal.

摘要翻译： 在用于接收FSK调制波的双超外差类型的FSK接收机中，包括用于确保锁相环产生第一本地振荡信号的PLL本地振荡器（10）和用于解调FSK调制波的解调部分（12） 使用第一本地振荡信号和第二本地振荡信号转换成解调信号，当解调信号具有指示与锁相中相位锁定的偏差的平均值时，控制信号产生电路（14）产生控制信号 循环。 在同步电路（16）连接到解调部分的同步电路（16）基于通过确定解调信号而获得的二进制数字信号建立位和帧同步，当建立位和帧同步时产生同步检测信号。 连接到PLL本地振荡器，控制信号产生电路和同步电路，间歇驱动电路（18）使得PLL本地振荡器基于控制信号和同步检测信号间歇地工作。

公开(公告)号：US5394109A

公开(公告)日：1995-02-28

申请号：US197912

申请日：1994-02-17

申请人： Frederic J. M. A. Simard

发明人： Frederic J. M. A. Simard

IPC分类号： H04L27/152 ,  H04L27/14

CPC分类号： H04L27/1525

摘要： A digital FSK demodulator includes a quadrature phase detector for detecting space and mark tones used in FSK signals. Due to its inherent characteristics, a telephone loop in which the demodulator is used produces unequal amplitudes in detected mark and space tones. The inequality or offset must be cancelled so that a proper timing signal can be recovered from the FSK signal. The demodulator includes a digital compensation circuit for off-hook and on-hook offset cancellation.

摘要翻译： 数字FSK解调器包括用于检测FSK信号中使用的空间和标记音的正交相位检测器。 由于其固有特性，使用解调器的电话回路在检测到的标记和空间音调中产生不等幅度。 必须取消不等式或偏移量，以便从FSK信号中恢复正确的定时信号。 解调器包括用于摘机和挂机偏移消除的数字补偿电路。