公开(公告)号：US5602848A

公开(公告)日：1997-02-11

申请号：US460951

申请日：1995-06-05

申请人： Lawrence P. Andrews ,  Gordon T. Davis ,  Lee H. House ,  Baiju D. Mandalia ,  Laurence V. Marks ,  William R. Robinson, Jr. ,  John C. Sinibaldi

发明人： Lawrence P. Andrews ,  Gordon T. Davis ,  Lee H. House ,  Baiju D. Mandalia ,  Laurence V. Marks ,  William R. Robinson, Jr. ,  John C. Sinibaldi

IPC分类号： H04Q11/04 ,  H04J3/12

CPC分类号： H04Q11/04 ,  H04Q2213/1305 ,  H04Q2213/13097 ,  H04Q2213/13103 ,  H04Q2213/13213 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/1336

摘要： A multi-mode time division multiplexing (TDM) interface circuit for interfacing between a serial data port and a data buffer is provided. The TDM interface circuit contains a transmitter and a receiver section. The circuit is programmable to operate in a variety of modes and is capable of supporting various multi-channel TDM interfaces as well as single channel analog interfaces. The circuit is programmable by writing a control word to a control register. In operation the circuit receives a frame synchronization signal, a gated bit clock signal, and a bit clock signal from the circuit with which it is interfacing on the serial data port. A base address input to a base address register provides up to 9 of the most significant bits of a data buffer address. A 12-bit counter is used to generate the remaining (least significant) bits of the data buffer address according to the control word in the control register.

摘要翻译： 提供了用于在串行数据端口和数据缓冲器之间进行接口的多模式时分复用（TDM）接口电路。 TDM接口电路包含发射机和接收机部分。 该电路可编程为以各种模式工作，并且能够支持各种多通道TDM接口以及单通道模拟接口。 该电路通过将控制字写入控制寄存器来编程。 在操作中，电路从串行数据端口接口的电路接收帧同步信号，门控位时钟信号和位时钟信号。 输入到基地址寄存器的基地址最多可以提供数据缓冲区地址的最高有效位的9位。 根据控制寄存器中的控制字，使用12位计数器产生数据缓冲器地址的剩余（最低有效位）。

公开(公告)号：US5491720A

公开(公告)日：1996-02-13

申请号：US887433

申请日：1992-05-21

申请人： Gordon T. Davis ,  Judith M. Linger ,  Baiju D. Mandalia ,  John C. Sinibaldi ,  William M. Zevin ,  Karl-Heinz Ziegenhain

发明人： Gordon T. Davis ,  Judith M. Linger ,  Baiju D. Mandalia ,  John C. Sinibaldi ,  William M. Zevin ,  Karl-Heinz Ziegenhain

IPC分类号： H04L25/02 ,  H04L27/00 ,  H04L29/06 ,  H04B1/38

CPC分类号： H04L29/06 ,  H04L25/0262 ,  H04L27/0012 ,  H04L69/18

摘要： A method and system in a data communications system for automatically determining a data communication device type and a transmission speed associated with the data communication device type. An incoming communication is detected on a transmission line, and transmit and receive hardware are connected to the transmission line. Next, a sequence of different signals in either a first communication protocol or a second communication protocol are transmitted from a first data communication device via a transmission line. The transmission line is then monitored for a response signal from a second data communication device. The response signal is initiated from the second data communication device in response to receipt of a particular signal within the transmitted sequence of different signals. Utilizing the relationship between the response signal and the transmitted sequence of different signals, a data communication device type and transmission speed are determined, and data communications may then be established between the first data communication device and the second data communication device at an optimal transmission speed.

摘要翻译： 一种用于自动确定与数据通信设备类型相关联的数据通信设备类型和传输速度的数据通信系统中的方法和系统。 在传输线上检测到进入通信，并且发送和接收硬件连接到传输线。 接下来，通过传输线从第一数据通信设备发送第一通信协议或第二通信协议中的不同信号的序列。 然后监测传输线路的来自第二数据通信设备的响应信号。 响应于响应于在所发送的不同信号序列内的特定信号的接收，响应信号从第二数据通信设备发起。 利用响应信号和不同信号的发送序列之间的关系，确定数据通信设备类型和传输速度，然后可以以最佳传输速度在第一数据通信设备和第二数据通信设备之间建立数据通信 。

公开(公告)号：US5420888A

公开(公告)日：1995-05-30

申请号：US886676

申请日：1992-05-21

申请人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi

发明人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi

IPC分类号： H04L27/152 ,  H04L27/14

CPC分类号： H04L27/1525

摘要： A system and method for efficient operation of a digital signal processor allows execution of a noncoherent FSK demodulation process at the baud rate of the incoming signal. First and second signal detecting channels terminate at a summing junction. A signal sampler for applying a sampled signal to the first and second signal detecting channels. The first and second signal detecting channels each include, in series, a finite impulse response filter for filtering out energy outside a selected bandwidth, automatic gain control and a demodulator. The finite impulse response filter means for the second signal detecting channel further shifts the phase of the sampled signal in the second signal detecting channel approximately 90 degrees relative to the sampled signal in the first signal detecting channel. The demodulator in each signal detecting channel further includes first and second sampled signal transmission paths terminating in a multiplying junction. The first signal transmission path in each demodulator includes a tunable delay line. The decoder takes its input from the summing junction for reproducing a signal indicating presence of a particular frequency or reproduction of the baseband signal.

摘要翻译： 用于数字信号处理器的有效操作的系统和方法允许以输入信号的波特率执行非相干FSK解调过程。 第一和第二信号检测通道终止于加法结。 一种用于将采样信号施加到第一和第二信号检测通道的信号采样器。 第一和第二信号检测通道各自包括用于滤出选定带宽以外的能量的有限脉冲响应滤波器，自动增益控制和解调器。 用于第二信号检测通道的有限脉冲响应滤波器装置进一步使第二信号检测通道中的采样信号的相位相对于第一信号检测通道中的采样信号大约90度。 每个信号检测信道中的解调器还包括终止于乘法结的第一和第二采样信号传输路径。 每个解调器中的第一信号传输路径包括可调延迟线。 解码器从加法结接收其输入，以再现指示特定频率的存在或基带信号的再现的信号。

公开(公告)号：US5263054A

公开(公告)日：1993-11-16

申请号：US886674

申请日：1992-05-21

申请人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi ,  William M. Zevin

发明人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi ,  William M. Zevin

IPC分类号： H04L25/05 ,  H04L25/38 ,  H04L27/06

CPC分类号： H04L25/05

摘要： An apparatus for efficient computation of a demodulation process on a digital signal processor for a sampled signal, which includes programming a digital signal processor to apply the sampled signal to an interpolating filter to add interpolation samples to the sampled signal, to search the sampled signal for a threshold crossing associated with a start bit, performing a linear interpolation to find a point where the threshold crossing occurs when a threshold crossing is detected, responsive to determining the point of the threshold crossing, determining a center of a start bit when the point of the threshold crossing has been determined, calculating a supplemental delay, and determining center points for subsequent of data bits utilizing the supplemental delay period from the center of the start bit.

摘要翻译： 一种用于对采样信号的数字信号处理器进行解调处理的有效计算的装置，其包括对数字信号处理器进行编程以将采样信号施加到内插滤波器以将采样信号加到采样信号中， 与开始位相关联的阈值交叉，执行线性内插，以在检测到阈值交叉时发现阈值交叉发生的点，响应于确定阈值交叉点，确定起点的中心，当点 已经确定了阈值交叉，计算补充延迟，并且利用来自起始位的中心的补充延迟周期来确定随后的数据位的中心点。

公开(公告)号：US5572695A

公开(公告)日：1996-11-05

申请号：US250974

申请日：1994-05-31

申请人： Lawrence P. Andrews ,  Derrick L. Arias ,  Judith M. Linger ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi

发明人： Lawrence P. Andrews ,  Derrick L. Arias ,  Judith M. Linger ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi

IPC分类号： G06F15/16 ,  G06F12/02 ,  G06F15/167

CPC分类号： G06F12/0284 ,  H04Q2213/13103 ,  H04Q2213/13107 ,  H04Q2213/1332 ,  H04Q2213/13396

摘要： A digital signal processing system includes first and second logical memory mapping units coupled to first and second digital processors respectively and to a data storage unit. The system further includes first and second mapping registers for containing first and second address mapping information coupled to the first and second digital processors respectively. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.

摘要翻译： 数字信号处理系统包括分别耦合到第一和第二数字处理器的第一和第二逻辑存储器映射单元以及数据存储单元。 该系统还包括第一和第二映射寄存器，用于分别包含耦合到第一和第二数字处理器的第一和第二地址映射信息。 第一和第二映射单元用于分别接收（i）分别由第一和第二数字处理器生成的第一和第二逻辑地址，以及（ii）第一和第二地址映射信息，并且生成第一和第二物理地址， 数字处理器可以独立地访问数据存储单元内的多个存储器位置中的任何一个。

公开(公告)号：US5634099A

公开(公告)日：1997-05-27

申请号：US352953

申请日：1994-12-09

申请人： Lawrence P. Andrews ,  Derrick Arias ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi ,  Kevin B. Williams

发明人： Lawrence P. Andrews ,  Derrick Arias ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi ,  Kevin B. Williams

IPC分类号： G06F13/28 ,  G06F15/17

CPC分类号： G06F13/28

摘要： There is provided a Direct Access Memory Unit (DAu) that is associated with a remote processor module in a multi-processing system. The DAU performs Direct Memory Access (DMA) operations independently of a Central Processing Unit (CPU) in the remote processor module. The CPU requests a DMA by writing information relevant to the DMA to the remote processor's memory. The address of each control block is written to a circular queue, also in the remote processor's memory. The DAU determines if there are any control blocks to process and if so, the DAU will perform the DMA operation (reading data from or writing data to the memory of the host processor), all without the intervention of the CPU of the remote processor module. The CPU adds a new control block by loading its address in a location in the circular queue that is ahead of the circular queue location that the DAU is processing. The CPU can abort a pending DMA request during DAU operations by setting a skip bit in the control block. Upon the completion of performing a DMA request, the DAU will set a complete bit in the control block in the remote processor's memory. An interrupt can also be sent to the CPU, wherein the CPU is advised that a DMA request has been completed. The data in a DMA operation is sent in bursts to a buffer located between two busses having different data transmission rates.

摘要翻译： 提供了与多处理系统中的远程处理器模块相关联的直接存取存储器单元（DAu）。 DAU独立于远程处理器模块中的中央处理器（CPU）执行直接存储器访问（DMA）操作。 CPU通过将与DMA有关的信息写入远程处理器的内存来请求DMA。 每个控制块的地址也写入循环队列，也在远程处理器的内存中。 DAU确定是否有任何控制块进行处理，如果是这样，则DAU将执行DMA操作（从主机处理器的存储器读取数据或向主机处理器写入数据），而无需远程处理器模块的CPU的干预 。 CPU通过将其地址加载到循环队列中位于DAU正在处理的循环队列位置之前的位置来添加新的控制块。 CPU可以在DAU操作期间通过设置控制块中的跳过位来中止待处理的DMA请求。 在执行DMA请求完成后，DAU将在远程处理器的存储器中的控制块中设置完整的位。 中断也可以发送到CPU，其中建议CPU已经完成了DMA请求。 DMA操作中的数据以突发方式发送到位于具有不同数据传输速率的两个总线之间的缓冲器。

公开(公告)号：US5553293A

公开(公告)日：1996-09-03

申请号：US353016

申请日：1994-12-09

申请人： Lawrence P. Andrews ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi ,  Kevin B. Williams ,  Christopher D. Touch

发明人： Lawrence P. Andrews ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi ,  Kevin B. Williams ,  Christopher D. Touch

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interprocessor interrupt hardware unit ("IIU") for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off loads tasks involved in processing interrupts from the operating kernel of the remote processor. Control blocks of interrupt information and commands are stored in Data Random Access Memory (DRAM) by the remote processor. The remote processor sets up a buffer of control block memory addresses in DRAM for the IIU to access to retrieve the control blocks from DRAM. The IIU retrieves a control block and loads the control block into registers. The IIU then issues an interrupt request to the host processor. The host processor receives the interrupt request and reads the registers to obtain the control block. The host processor clears the interrupt request and indicates to the IIU that the interrupt has been processed. The IIU then notifies the remote processor that the interrupt has been processed. The IIU may be programmed to notify the remote processor of completion either by an interrupt or by setting a status flag in the DRAM.

摘要翻译： 处理器中断硬件单元（“IIU”），用于处理多处理器系统上的远程处理器和主机处理器之间的中断。 IIU负载处理来自远程处理器的操作内核的中断的任务。 中断信息和命令的控制块由远程处理器存储在数据随机存取存储器（DRAM）中。 远程处理器在DRAM中设置控制块存储器地址的缓冲器，用于IIU以访问以从DRAM中检索控制块。 IIU检索一个控制块，并将控制块加载到寄存器中。 然后，IIU向主机处理器发出中断请求。 主机处理器接收中断请求并读取寄存器以获取控制块。 主处理器清除中断请求，并向IIU指示中断已被处理。 然后，IIU通知远处理器中断已被处理。 IIU可以被编程为通过中断或通过在DRAM中设置状态标志来通知远程处理器完成。

公开(公告)号：US4871974A

公开(公告)日：1989-10-03

申请号：US289064

申请日：1988-12-23

申请人： Gordon T. Davis ,  Baiju D. Mandalia

发明人： Gordon T. Davis ,  Baiju D. Mandalia

IPC分类号： H04L27/22 ,  H04L27/227

CPC分类号： H04L27/2275

摘要： A demodulator mechanism which uses estimates of the in-phase and quadrature-phase components of differential phase modulated carrier signals for performing a coherent demodulation of these signals is described. The instantaneous estimates, obtained from an estimator circuit, are fed into a differential carrier recovery circuit, which provides for a feedback of ideal sine and cosine components, and combined with the instantaneous estimates for incrementally decreasing a phase error signal generated in a computational circuit. By thus incrementally decreasing the phase error signal, an ideal phase angle is eventually obtained, thereby providing for coherent demodulated output components of the input carrier signals.

公开(公告)号：US4991169A

公开(公告)日：1991-02-05

申请号：US227832

申请日：1988-08-02

申请人： Gordon T. Davis ,  Michael G. Ho Lung ,  Baiju D. Mandalia ,  Roland J. Millas ,  Oscar E. Ortega ,  Rafael J. Picon ,  Loran R. Queen ,  Richard H. Robinson ,  William R. Robinson, Jr. ,  Leo A. Sharp, Jr. ,  Jan W. van den Berg

发明人： Gordon T. Davis ,  Michael G. Ho Lung ,  Baiju D. Mandalia ,  Roland J. Millas ,  Oscar E. Ortega ,  Rafael J. Picon ,  Loran R. Queen ,  Richard H. Robinson ,  William R. Robinson, Jr. ,  Leo A. Sharp, Jr. ,  Jan W. van den Berg

IPC分类号： H04M11/06 ,  H04J3/12

CPC分类号： H04J3/12 ,  H04Q2213/13034 ,  H04Q2213/1309 ,  H04Q2213/13103 ,  H04Q2213/13107 ,  H04Q2213/13174 ,  H04Q2213/13199 ,  H04Q2213/13213 ,  H04Q2213/13215 ,  H04Q2213/13292 ,  H04Q2213/13377 ,  H04Q2213/13396

摘要： A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the most processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, selective routing of voice to host storage for voice mail applications, etc.).

公开(公告)号：US5459843A

公开(公告)日：1995-10-17

申请号：US282412

申请日：1994-07-28

申请人： Gordon T. Davis ,  Sebastian T. Ventrone ,  John J. Reilly ,  Baiju D. Mandalia ,  Michael G. Holung ,  William R. Robinson, Jr.

发明人： Gordon T. Davis ,  Sebastian T. Ventrone ,  John J. Reilly ,  Baiju D. Mandalia ,  Michael G. Holung ,  William R. Robinson, Jr.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3851

摘要： A pipelined, RISC-type processor operated in parallel mode and its associated processing methods for separately handling instructions from multiple program instruction sets. The pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times the cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions.

摘要翻译： 以并行模式运行的流水线RISC型处理器及其相关处理方法，用于分别处理来自多个程序指令集的指令。 流水线处理器包括指令提取单元，指令解码单元和n个执行单元。 每个执行单元以基本上相同的处理周期时间操作，而指令获取单元和指令解码单元的操作速度至少为执行单元的周期时间的n倍，使得流水线的每个相分别基本上处理n个指令 在一个机器周期内。 定时和控制电路耦合到每个主要元件单元，用于控制指令上的操作的时序和顺序。