公开(公告)号：US20190392110A1

公开(公告)日：2019-12-26

申请号：US16013403

申请日：2018-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gazi M. Huda ,  Samuel O. Nakagawa

IPC: G06F17/50 ,  H01L27/02 ,  H01L21/321

Abstract: The disclosure provides a method including: identifying a fill-dense region of an integrated circuit (IC) layout having a plurality of fill cells, and a target fill region of the IC layout adjacent to the fill-dense region and free of fill cells; modifying the IC layout by removing a fill cell from the fill-dense region and inserting a duplicate of the removed fill cell within the target fill region to at least partially fill the target fill region; and providing instructions to manufacture an IC using the modified IC layout. The method may reduce a feature density of the fill-dense region to less than an allowable feature density, while adding fill features to otherwise unfillable regions.

公开(公告)号：US10516767B2

公开(公告)日：2019-12-24

申请号：US15131174

申请日：2016-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amith Singhee ,  Steven Hirsch ,  Ashok Pon Kumar Sree Prakash ,  Ulrich A. Finkler ,  David O. Melville ,  Scott M. Mansfield

IPC: G06F15/173 ,  H04L29/06 ,  H04L29/08

Abstract: A method of presenting data over a Web service interface includes: establishing, by a first computer process, a persistent transmission control protocol (TCP) network connection between the first computer process and a second computer process; dynamically allocating, by the second computer process, memory in response to receipt of static data over the persistent TCP network connection from the first computer process; updating, by the second computer process, the memory in response to receipt of dynamic data received over the persistent TCP network connection from the first computer process; and enabling, by the second computer process, a Web server to access the updated data for presentation by the Web service interface. The static data identifies a given entity and the dynamic data includes metric data provided for the entity.

公开(公告)号：US10510749B1

公开(公告)日：2019-12-17

申请号：US16057881

申请日：2018-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos ,  Garo J. Derderian

IPC: H01L29/76 ,  H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06

Abstract: A resistor for an integrated circuit (IC), an IC and a related method are disclosed. The resistor may include a metal alloy resistor body positioned within a single diffusion break (SDB). The SDB provides an isolation region in a semiconductor fin between a pair of fin-type field effect transistors (finFETs). The resistor in the SDB allows for the resistor to be built at front-end-of-line (FEOL) layers, which saves on space and expense, and allows for precise dimensions for the resistor.

公开(公告)号：US20190379338A1

公开(公告)日：2019-12-12

申请号：US16550385

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： See T. Lee ,  Abdellatif Bellaouar

IPC: H03F1/56 ,  H03B5/12 ,  H03F3/193 ,  H03F3/24

Abstract: In an exemplary structure, a transformer has a primary side and a secondary side. Output from the primary side is coupled to the secondary side. A first power supply is connected to a center tap of the primary side of the transformer. An oscillator includes a first transistor and a second transistor. The front-gate of the first transistor is connected to the drain of the second transistor and the primary side of the transformer. The front-gate of the second transistor is connected to the drain of the first transistor and the primary side of the transformer. A third transistor is connected to the first transistor and a fourth transistor is connected to the second transistor. The third and fourth transistors inject a desired frequency to the oscillator. A voltage source is connected to the back-gate of the first transistor and the back-gate of the second transistor.

公开(公告)号：US20190378900A1

公开(公告)日：2019-12-12

申请号：US16548335

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45

Abstract: One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.

公开(公告)号：US20190355730A1

公开(公告)日：2019-11-21

申请号：US15983627

申请日：2018-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul

IPC: H01L27/11

Abstract: Structures for a static random access memory (SRAM) bitcell and methods for forming a SRAM bitcell. The SRAM includes a storage element with a first pull-up (PU) vertical-transport field-effect transistor (VTFET) having a first bottom source/drain region and a fin projecting from the first bottom source/drain region, and a second pull-up (PU) VTFET with a second bottom source/drain region and a fin projecting from the second bottom source/drain region. The fin of the first PU VTFET is arranged over a first active region in which the first bottom source/drain region is centrally arranged, and the fin of the second PU VTFET is arranged over a second active region in which the second bottom source/drain region is centrally arranged. The second source/drain region is aligned with the first bottom source/drain region. A read port may be connected with the storage element, and may also be formed using VTFETs.

公开(公告)号：US20190355615A1

公开(公告)日：2019-11-21

申请号：US16525601

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

公开(公告)号：US20190355402A1

公开(公告)日：2019-11-21

申请号：US15983263

申请日：2018-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wuyang HAO ,  Jack T. WONG ,  Chunsung CHIANG

IPC: G11C11/16

Abstract: The present disclosure relates to a structure which includes a merged write driver circuit with a first device next to a first memory array and a second device next to a second memory array, and the merged write driver circuit being configured to share a write driver line between the first device and the second device.

公开(公告)号：US10483943B2

公开(公告)日：2019-11-19

申请号：US15634397

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vincent J. McGahay ,  Bhupesh Chandra

IPC: H03H9/56 ,  H01L41/18 ,  H03H3/08 ,  H01L41/257 ,  H03H3/02 ,  H03H9/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to artificially oriented piezoelectric films for integrated filters and methods of manufacture. The structure includes: a piezoelectric film with effective crystalline orientations of the polar axis rotated 90 degrees from a natural orientation for planar deposited films; and a conductor pattern formed on a surface of the piezoelectric film.

公开(公告)号：US10483917B2

公开(公告)日：2019-11-19

申请号：US16428842

申请日：2019-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： See Taur Lee ,  Abdellatif Bellaouar

IPC: H03F1/02 ,  H03F3/193 ,  H04B1/04 ,  H03F3/21 ,  H03F3/45

Abstract: We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.