公开(公告)号：US11545899B2

公开(公告)日：2023-01-03

申请号：US16860862

申请日：2020-04-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Nonaka

IPC: H02M3/157 ,  H02M3/158 ,  H02M1/36

Abstract: To provide a semiconductor device with a digital-controlled DC-DC converter capable of stable feedback operation while minimizing area, the semiconductor device includes a DC-DC converter whose characteristic is determined by the control parameter, a flash memory and a processor that controls the flash memory, both of which operate at a power supply based on the output of the DC-DC converter. The control parameter is stored in the flash memory, and the control parameter is read out from the flash memory and set in the DC-DC converter by the processor while the DC-DC converter is operating.

公开(公告)号：US20220416079A1

公开(公告)日：2022-12-29

申请号：US17901416

申请日：2022-09-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Machiko SATO ,  Akihiro SHIMOMURA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.

公开(公告)号：US20220406936A1

公开(公告)日：2022-12-22

申请号：US17897844

申请日：2022-08-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO ,  Shiro KAMOHARA

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20220406700A1

公开(公告)日：2022-12-22

申请号：US17722823

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuhiro KINOSHITA ,  Shuuichi KARIYAZAKI ,  Keita TSUCHIYA

IPC: H01L23/498 ,  H01L23/66

Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. Also, the first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. Also, the second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

公开(公告)号：US11526452B2

公开(公告)日：2022-12-13

申请号：US17400918

申请日：2021-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi Ichikawa

IPC: G06F12/14 ,  G06F9/455

Abstract: To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.

公开(公告)号：US11526137B2

公开(公告)日：2022-12-13

申请号：US16732036

申请日：2019-12-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Suzaki ,  Toshihiro Kawano

IPC: G05B9/02 ,  G06F3/06 ,  G06F11/07

Abstract: In the conventional semiconductor device, it is impossible for two CPUs to operate memories to be debugged at synchronous timings. According to one embodiment, the operation verifying program analyzes the operation verifying command received by the first semiconductor device 10 from the external device 31 by its own device (S32), transfers the operation verifying command to the second semiconductor device 20 (S31, S41), also analyzes the operation verifying command in the second semiconductor device 20 (S42), outputs the trigger signal (S34, S44) to the first semiconductor device 10 from the second semiconductor device 20 based on the result of the analysis, writes the memory setting values included in the operation verifying command to the memories in the respective semiconductor device (S35, S45) based on the trigger signal, and restarts the device operation based on the written memory setting values.

公开(公告)号：US20220386239A1

公开(公告)日：2022-12-01

申请号：US17748716

申请日：2022-05-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki SUGIMOTO ,  Kenji OGAMI

IPC: H04W52/02 ,  H04W52/36

Abstract: An active period that is expressed by a range of a count value t[x] and is a period during which communication of a packet with an outside is permitted and an inactive period that is expressed by a range of the count value t[x] and is a period during which communication of a packet with an outside is prohibited are defined in schedule data. A wireless communication interface communicates a packet with the outside during the active period. A power supply controller cuts off power supplied to the wireless communication interface during the inactive period. A synchronous controller updates a count value of a counter based on a synchronous data value in the received packet during a reception operation of the packet, define the synchronous data value based on the updated count value t[y] during a transmission operation of the packet, and store it in the packet to be transmitted.

公开(公告)号：US20220376040A1

公开(公告)日：2022-11-24

申请号：US17717724

申请日：2022-04-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion which is integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, a high dielectric constant film in contact with the step insulating film and having a higher dielectric constant than silicon.

公开(公告)号：US20220374206A1

公开(公告)日：2022-11-24

申请号：US17722763

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuhiko FUKUSHIMA ,  Kazuo ASAMI

IPC: G06F7/58

Abstract: A semiconductor device and a method of verifying random number data capable of preventing erroneous judgement of data having periodicity as a random number and verifying randomness of random number data with high accuracy are provided. The semiconductor device includes a random number generator for generating random number data as serial data, and a health test circuit for verifying randomness of the random number data. The health test circuit handles the random number data as a data string of n-bit data by dividing the random number data by n bits (n is an integer larger than or equal to two). and verifies randomness based on the n-bit data.

公开(公告)号：US11494327B2

公开(公告)日：2022-11-08

申请号：US17169708

申请日：2021-02-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Manabu Koike

IPC: G06F13/36 ,  G06F13/372 ,  G06F13/42 ,  G06F13/374 ,  G06F13/40

Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.