中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

227 records (took 0.019 seconds)

    Transitional interface between metal and dielectric in interconnect structures
    141.
    发明授权
    Transitional interface between metal and dielectric in interconnect structures 有权
    互连结构中金属和电介质之间的过渡界面

    公开(公告)号：US07777344B2

    公开(公告)日：2010-08-17

    申请号：US11786241

    申请日：2007-04-11

    Applicant: Chien-Hsueh Shih ,  Shau-Lin Shue

    Inventor： Chien-Hsueh Shih ,  Shau-Lin Shue

    IPC: H01L23/52

    CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

    Abstract translation: 提供一种集成电路结构及其形成方法。 集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的开口; 开口中的导电线; 覆盖导线的金属合金层; 覆盖在金属合金层上的第一金属硅化物层; 以及与第一金属硅化物层上的第一金属硅化物层不同的第二金属硅化物层。 金属合金层和第一和第二金属硅化物层基本上垂直对准导电线。

    Cleaning processes in the formation of integrated circuit interconnect structures
    142.
    发明授权
    Cleaning processes in the formation of integrated circuit interconnect structures 有权
    形成集成电路互连结构的清洁过程

    公开(公告)号：US07700479B2

    公开(公告)日：2010-04-20

    申请号：US11593286

    申请日：2006-11-06

    Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC: H01L21/4763

    CPC classification number: H01L21/02063 ,  H01L21/76807 ,  H01L21/76814

    Abstract: A method for fabricating an integrated circuit includes providing a substrate, forming a low-k dielectric layer over the substrate, etching the low-k dielectric layer to form an opening in the low-k dielectric layer wherein an underlying metal is exposed through the opening, performing a remote plasma treatment to the substrate wherein a plasma used for the remote plasma treatment is generated from a plasma generator separated from a chamber in which the substrate is located, forming a diffusion barrier layer in the opening, and filling the opening with a conductive material. The method preferably includes an in-situ plasma treatment in a same chamber as the step of etching the low-k dielectric layer.

    Abstract translation: 一种用于制造集成电路的方法包括提供衬底，在衬底上形成低k电介质层，蚀刻低k电介质层以在低k电介质层中形成开口，其中下面的金属通过开口暴露 对基板执行远程等离子体处理，其中用于远程等离子体处理的等离子体从与其中所述基板所在的室分离的等离子体发生器产生，在该开口中形成扩散阻挡层，并且在该开口中填充该开口 导电材料。 该方法优选包括在与蚀刻低k电介质层的步骤相同的室中的原位等离子体处理。

    Work function adjustment on fully silicided (FUSI) gate
    145.
    发明授权
    Work function adjustment on fully silicided (FUSI) gate 有权
    完全硅化（FUSI）门的功能调整

    公开(公告)号：US07501333B2

    公开(公告)日：2009-03-10

    申请号：US11458503

    申请日：2006-07-19

    Applicant: Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    Inventor： Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC: H01L21/44

    CPC classification number: H01L21/28097 ,  H01L29/4975 ,  H01L29/517

    Abstract: A fully silicided gate with a selectable work function includes; a gate dielectric over the substrate; and a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.

    Abstract translation: 具有可选工作功能的完全硅化栅包括： 衬底上的栅极电介质; 以及在所述栅极电介质上的第一金属硅化物层，以及第二金属硅化物层，其中所述第一金属硅化物具有与所述第二金属硅化物层不同的相。 金属硅化物层包括至少一种合金元素。 栅极电介质和金属硅化物层之间的界面上的合金元素的浓度影响栅极的功函数。

    SEMICONDUCTOR MEMORY STRUCTURES
    146.
    发明申请
    SEMICONDUCTOR MEMORY STRUCTURES 有权
    半导体存储器结构

    公开(公告)号：US20080290467A1

    公开(公告)日：2008-11-27

    申请号：US11752736

    申请日：2007-05-23

    Applicant: Shau-Lin Shue ,  Chao-An Jong

    Inventor： Shau-Lin Shue ,  Chao-An Jong

    IPC: H01L29/94 ,  H01L29/12

    CPC classification number: H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

    Abstract: A semiconductor structure includes a first conductive layer coupled to a transistor. A first dielectric layer is over the first conductive layer. A second conductive layer is within the first dielectric layer, contacting a portion of a top surface of the first conductive layer. The second conductive layer includes a cap portion extending above a top surface of the first dielectric layer. A first dielectric spacer is between the first dielectric layer and the second conductive layer. A phase change material layer is above a top surface of the second conductive layer. A third conductive layer is over the phase change material layer. A second dielectric layer is over the first dielectric layer. A second dielectric spacer is on a sidewall of the cap portion, wherein a thermal conductivity of the second dielectric spacer is less than that of the first dielectric layer or that of the second dielectric layer.

    Abstract translation: 半导体结构包括耦合到晶体管的第一导电层。 第一电介质层在第一导电层之上。 第二导电层在第一介电层内，与第一导电层的顶表面的一部分接触。 第二导电层包括在第一介电层的顶表面上方延伸的盖部分。 第一介电隔离物在第一介电层和第二导电层之间。 相变材料层在第二导电层的顶表面之上。 第三导电层在相变材料层之上。 第二电介质层在第一介电层上。 第二电介质间隔物位于帽部分的侧壁上，其中第二电介质间隔物的热导率小于第一电介质层或第二电介质层的热导率。

    Method for silicide formation on semiconductor devices
    147.
    发明授权
    Method for silicide formation on semiconductor devices 有权
    在半导体器件上形成硅化物的方法

    公开(公告)号：US07446042B2

    公开(公告)日：2008-11-04

    申请号：US11343648

    申请日：2006-01-30

    Applicant: Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    Inventor： Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC: H01L21/44

    CPC classification number: H01L21/28518

    Abstract: A method for forming nickel silicide includes degassing a semiconductor substrate that includes a silicon surface. After the degassing operation, the substrate is cooled prior to a metal deposition process, during a metal deposition process, or both. The cooling suppresses the temperature of the substrate to a temperature less than the temperature required for the formation of nickel silicide. Nickel diffusion is minimized during the deposition process. After deposition, an annealing process is used to urge the formation of a uniform silicide film. In various embodiments, the metal film may include a binary phase alloy containing nickel and a further element.

    Abstract translation: 一种形成硅化镍的方法包括对包含硅表面的半导体衬底脱气。 在脱气操作之后，在金属沉积工艺，金属沉积工艺期间或两者之间冷却基板。 冷却将基板的温度抑制到低于形成硅化镍所需的温度的温度。 在沉积过程中镍的扩散最小化。 沉积后，使用退火工艺来促使形成均匀的硅化物膜。 在各种实施例中，金属膜可以包括含有镍和另一元素的二元相合金。

    Semiconductor structure including silicide regions and method of making same
    148.
    发明授权
    Semiconductor structure including silicide regions and method of making same 有权
    包括硅化物区域的半导体结构及其制造方法

    公开(公告)号：US07396767B2

    公开(公告)日：2008-07-08

    申请号：US10892915

    申请日：2004-07-16

    Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

    Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC: H01L21/44

    CPC classification number: H01L29/66507 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908

    Abstract: A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

    Abstract translation: 一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

Patent Agency Ranking