公开(公告)号：US09087881B2

公开(公告)日：2015-07-21

申请号：US13785934

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean X. Lin ,  Xunyuan Zhang ,  Ming He ,  Larry Zhao ,  John Iacoponi ,  Kunaljeet Tanwar

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76847 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract translation: 在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。 铜屏障通过屏障上的铜生长促进衬里将沟槽排列。 沟槽有大量铜填充，并且在铜中包括空隙。 具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。 浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

公开(公告)号：US20150200353A1

公开(公告)日：2015-07-16

申请号：US14156210

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Hyun-Jin Cho

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L43/12

Abstract: Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer. By forming the MJT between the metal layers using only one or two masks, the overall number of processing steps is reduced.

Abstract translation: 本文的实施例提供了形成在半导体器件的金属层之间的磁性隧道结（MTJ）。 具体地，提供了仅使用一个或两个掩模形成半导体器件的方法，所述方法包括：在所述半导体器件的电介质层中形成第一金属层，在所述第一金属层上形成底电极层，形成MTJ 在所述底部电极层上方，在所述MTJ上形成顶部电极层，用第一掩模图案化所述顶部电极层和所述MTJ，以及在所述顶部电极层上方形成第二金属层。 可选地，可以使用第二掩模对底部电极层进行图案化。 此外，在另一个实施例中，绝缘体层（例如，锰）形成在电介质层的顶部，其中第一金属层的顶表面在形成绝缘体层之后保持暴露，使得底部电极层接触绝缘层的顶表面 第一金属层。 通过仅使用一个或两个掩模在金属层之间形成MJT，减少了处理步骤的总数。

公开(公告)号：US09059255B2

公开(公告)日：2015-06-16

申请号：US13781921

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76868 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料层上形成由多个间隔开的导电结构构成的非连续层，其中部分 未被多个间隔开的导电结构覆盖的绝缘材料层保持暴露，在非连续层上形成至少一个阻挡层，其中阻挡层接触间隔开的导电结构和该层的暴露部分 绝缘材料，在阻挡层上形成至少一个衬垫层，以及在衬里层上方的沟槽/通孔中形成导电结构。

公开(公告)号：US09040421B2

公开(公告)日：2015-05-26

申请号：US13887174

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.

Abstract translation: 提供了制造集成电路的方法。 在示例性实施例中，用于制造集成电路的方法包括提供在其中和/或其上设置有器件的半导体衬底。 包括阻挡层和覆盖阻挡层的插塞金属的接触结构形成为与器件电接触。 覆盖接触结构的硬掩模形成。 该方法包括执行蚀刻以形成通过硬掩模的通孔，并暴露阻挡层和插塞金属。 此外，该方法用湿蚀刻剂去除硬掩模的剩余部分，而接触结构被配置为抑制湿蚀刻剂蚀刻阻挡层。 在该方法中，通孔开口填充有导电材料以形成与接触结构的互连。

公开(公告)号：US20150137373A1

公开(公告)日：2015-05-21

申请号：US14081749

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

Abstract translation: 提供具有改进的接触结构的集成电路和用于制造具有改进的接触结构的集成电路的方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底内和/或半导体衬底上提供器件。 此外，该方法包括形成与该装置电接触的接触结构。 接触结构包括覆盖该装置的硅酸盐阻挡部分，覆盖该装置并且位于硅酸盐阻挡部分之间的阻挡金属以及覆盖该阻挡金属并位于硅酸盐阻挡部分之间的填充金属。

公开(公告)号：US20150108647A1

公开(公告)日：2015-04-23

申请号：US14061319

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Moosung Chae ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.

Abstract translation: 一种用于制造集成电路的方法包括提供覆盖半导体衬底的导电材料和覆盖导电材料的电介质材料，其中开口暴露导电材料的表面和电介质材料的侧壁，并选择性地沉积第一层 导电材料的表面上的阻挡材料，其中电介质材料的侧壁保持暴露，第一阻挡材料使得如果在退火过程中退火，则第一阻挡材料将扩散到导电材料中。 该方法还包括修改暴露表面上的第一阻挡材料以形成第二阻挡材料，第二阻挡材料使得在退火过程期间，第二阻挡材料不会扩散到导电材料中并沉积第二阻挡层 沿着开口的侧壁的第一阻挡材料。 此外，该方法包括退火半导体衬底。 还公开了根据前述方法制造的集成电路。

公开(公告)号：US20150108577A1

公开(公告)日：2015-04-23

申请号：US14056144

申请日：2013-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

Abstract: Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

Abstract translation: 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

公开(公告)号：US08980740B2

公开(公告)日：2015-03-17

申请号：US13786627

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd Ryan ,  Xunyuan Zhang

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76814 ,  H01L21/76826 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.

Abstract translation: 公开了一种调制沉积在半导体衬底中凹陷特征的侧壁和底板上的阻挡层的厚度的工艺。 该方法包括通过在还原气氛中进行退火来改变其上沉积阻挡层的导电特征的表面，以及任选地另外地使形成凹陷特征的侧壁的电介质表面甲硅烷基化。

公开(公告)号：US20140361435A1

公开(公告)日：2014-12-11

申请号：US14470213

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US08883631B1

公开(公告)日：2014-11-11

申请号：US13905271

申请日：2013-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Xiuyu Cai

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76804

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.

Abstract translation: 本文公开的一种说明性方法包括在导电结构之上形成至少一层绝缘材料，形成由绝缘材料层上方的金属构成的图案化硬掩模，执行至少一个蚀刻工艺以在绝缘材料层中限定空腔 形成牺牲材料层以便过度填充空腔，执行至少一个平坦化处理以去除牺牲材料层和图案化的硬掩模的一部分，同时将牺牲材料层的剩余部分留在空腔内， 以及去除位于腔内的牺牲材料层的剩余部分。