公开(公告)号：US06707060B2

公开(公告)日：2004-03-16

申请号：US10145404

申请日：2002-05-13

Applicant: Gang Yu ,  Yong Cao

Inventor： Gang Yu ,  Yong Cao

IPC: H01L2906

CPC classification number: H01L27/307 ,  B82Y10/00 ,  H01L27/1446 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14667 ,  H01L27/14676 ,  H01L27/14687 ,  H01L27/28 ,  H01L27/285 ,  H01L27/30 ,  H01L27/308 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/0046 ,  H01L51/0047 ,  H01L51/0081 ,  H01L51/0583 ,  H01L51/0591 ,  H01L51/4206 ,  H01L51/424 ,  H01L51/4253 ,  Y02E10/549

Abstract: The present invention relates generally to fabricating two-terminal electric microswitches comprising thin semiconductor films and using these microswitches to construct column-row (x-y) addressable microswitch matrices. These microswitches are two terminal devices through which electric current and electric potential (or their derivatives or integrals) can be switched on and off by the magnitude or the polarity of the external bias. The microswitches are made from semiconducting thin films in a electrode/semiconductor/electrode, thin film configuration. Column-row addressable electric microswitch matrices can be made in large areas, with high pixel density. Such matrices can be integrated with a sensor layer with electronic properties which vary in response to external physical conditions (such as photon radiation, temperature, pressure, magnetic field and so on), thereby forming a variety of detector matrices.

Abstract translation: 本发明一般涉及制造包括薄半导体膜的两端电微型开关，并且使用这些微型开关来构造列行（x-y）可寻址微动开关矩阵。 这些微动开关是通过外部偏压的大小或极性将电流和电位（或其导数或积分）接通和断开的两个终端装置。 微型开关由电极/半导体/电极中的半导体薄膜制成，薄膜结构。 列行可寻址的电动微动开关矩阵可以在较大的区域中制成，具有较高的像素密度。 这样的矩阵可以与具有响应于外部物理条件（诸如光子辐射，温度，压力，磁场等）变化的电子特性的传感器层集成，从而形成各种检测器矩阵。

公开(公告)号：US06441395B1

公开(公告)日：2002-08-27

申请号：US09241656

申请日：1999-02-02

Applicant: Gang Yu ,  Yong Cao

Inventor： Gang Yu ,  Yong Cao

IPC: H01L3524

CPC classification number: H01L27/307 ,  B82Y10/00 ,  H01L27/1446 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14667 ,  H01L27/14676 ,  H01L27/14687 ,  H01L27/28 ,  H01L27/285 ,  H01L27/30 ,  H01L27/308 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/0046 ,  H01L51/0047 ,  H01L51/0081 ,  H01L51/0583 ,  H01L51/0591 ,  H01L51/4206 ,  H01L51/424 ,  H01L51/4253 ,  Y02E10/549

Abstract: The present invention relates generally to fabricating two-terminal electric microswitches comprising thin semiconductor films and using these microswitches to construct column-row (x-y) addressable microswitch matrices. These microswitches are two terminal devices through which electric current and electric potential (or their derivatives or integrals) can be switched on and off by the magnitude or the polarity of the external bias. The microswitches are made from semiconducting thin films in a electrode/semiconductor/electrode, thin film configuration. Column-row addressable electric microswitch matrices can be made in large areas, with high pixel density. Such matrices can be integrated with a sensor layer with electronic properties which vary in response to external physical conditions (such as photon radiation, temperature, pressure, magnetic field and so on), thereby forming a variety of detector matrices.

Abstract translation: 本发明一般涉及制造包括薄半导体膜的两端电微型开关，并且使用这些微型开关来构造列行（x-y）可寻址微动开关矩阵。 这些微动开关是通过外部偏压的大小或极性将电流和电位（或其导数或积分）接通和断开的两个终端装置。 微型开关由电极/半导体/电极中的半导体薄膜制成，薄膜结构。 列行可寻址的电动微动开关矩阵可以在较大的区域中制成，具有较高的像素密度。 这样的矩阵可以与具有响应于外部物理条件（诸如光子辐射，温度，压力，磁场等）变化的电子特性的传感器层集成，从而形成各种检测器矩阵。

公开(公告)号：US09911857B2

公开(公告)日：2018-03-06

申请号：US12915712

申请日：2010-10-29

Applicant: Chan-Long Shieh ,  Fatt Foong ,  Gang Yu

Inventor： Chan-Long Shieh ,  Fatt Foong ,  Gang Yu

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: A metal oxide semiconductor device including an active layer of metal oxide, a layer of gate dielectric, and a layer of low trap density material. The layer of low trap density material is sandwiched between the active layer of metal oxide and the layer of gate dielectric. The layer of low trap density material has a major surface parallel and in contact with a major surface of the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide. A second layer of low trap density material can optionally be placed in contact with the opposed major surface of the active layer of metal oxide so that a low trap density interface is formed with both surfaces of the active layer of metal oxide.

公开(公告)号：US09773824B2

公开(公告)日：2017-09-26

申请号：US15087716

申请日：2016-03-31

Applicant: Chan-Long Shieh ,  Gang Yu

Inventor： Chan-Long Shieh ,  Gang Yu

IPC: H01L27/146 ,  H01L27/12 ,  H01L33/00 ,  H01L33/44 ,  H01L33/46 ,  H01L33/62 ,  H01L33/64 ,  H01L27/15

CPC classification number: H01L27/14609 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14663 ,  H01L27/14692 ,  H01L27/156 ,  H01L33/0075 ,  H01L33/44 ,  H01L33/46 ,  H01L33/62 ,  H01L33/642 ,  H01L2933/0025 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2933/0075

Abstract: A method of fabricating a pixelated imager and structure including a substrate with a bottom contact layer and active element blanket layers deposited on the bottom contact layer. The blanket layers are separated into an array of active elements with trenches isolating adjacent active elements in the array. A dielectric passivation/planarization layer is positioned over the array of active elements. An array of active element readout circuits overlies the passivation/planarization layer above the trenches with one active element readout circuit coupled to each active element of the array of active elements. Each active element and coupled active element readout circuit defines a pixel and the array of active elements and the coupled array of active element readout circuits defines a pixelated imager, and the readout circuit coupled to each active element includes at least one TFT with an active channel comprising a metal-oxide semiconductor material.

公开(公告)号：US09614102B2

公开(公告)日：2017-04-04

申请号：US15080231

申请日：2016-03-24

Applicant: Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

Inventor： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/70 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.

公开(公告)号：US20160293769A1

公开(公告)日：2016-10-06

申请号：US15186628

申请日：2016-06-20

Applicant: Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Tian Xiao ,  Juergen Musolf

Inventor： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Tian Xiao ,  Juergen Musolf

IPC: H01L29/786 ,  H01L23/535 ,  H01L21/467 ,  H01L29/66 ,  H01L21/4763 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/7869 ,  H01L21/467 ,  H01L21/4763 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78696

Abstract: A method of fabricating a stable, high mobility metal oxide thin film transistor includes the steps of providing a substrate, positioning a gate on the substrate, and depositing a gate dielectric layer on the gate and portions of the substrate not covered by the gate. A multiple film active layer including a metal oxide semiconductor film and a metal oxide passivation film is deposited on the gate dielectric with the passivation film positioned in overlying relationship to the semiconductor film. An etch-stop layer is positioned on a surface of the passivation film and defines a channel area in the active layer. A portion of the multiple film active layer on opposite sides of the etch-stop layer is modified to form an ohmic contact and metal source/drain contacts are positioned on the modified portion of the multiple film active layer.

Abstract translation: 一种制造稳定的高迁移率金属氧化物薄膜晶体管的方法包括以下步骤：提供衬底，将栅极定位在衬底上，以及在栅极上沉积栅极电介质层，并且将衬底部分未被栅极覆盖。 包括金属氧化物半导体膜和金属氧化物钝化膜的多层膜活性层沉积在栅极电介质上，钝化膜位于与半导体膜的重叠关系中。 蚀刻停止层位于钝化膜的表面上并限定有源层中的沟道区。 在蚀刻停止层的相对侧上的多个膜有源层的一部分被修改以形成欧姆接触，并且金属源极/漏极触点位于多个膜有源层的修改部分上。

公开(公告)号：US09362413B2

公开(公告)日：2016-06-07

申请号：US14081130

申请日：2013-11-15

Applicant: Gang Yu ,  Chan-Long Shieh ,  Juergen Musolf ,  Fatt Foong ,  Tian Xiao

Inventor： Gang Yu ,  Chan-Long Shieh ,  Juergen Musolf ,  Fatt Foong ,  Tian Xiao

IPC: H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/02565 ,  H01L21/02664 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.

Abstract translation: 一种制造高迁移率半导体金属氧化物薄膜晶体管的方法，包括以下步骤：沉积半导体金属氧化物材料层，在MO材料层上沉积蚀刻停止材料的覆盖层，以及图案化源/漏层 包括将源极/漏极金属层蚀刻成定位成限定半导体金属氧化物层中的沟道区域的源极/漏极端子的蚀刻停止材料的覆盖层上的金属。 蚀刻停止材料至少在源极/漏极端子之下在垂直于覆盖层的平面的方向上导电，以在源极/漏极端子和半导体金属氧化物材料层之间提供电接触。 蚀刻停止材料也是化学稳固的，以在蚀刻工艺期间保护半导体金属氧化物沟道材料层。

公开(公告)号：US09318614B2

公开(公告)日：2016-04-19

申请号：US14071644

申请日：2013-11-05

Applicant: Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

Inventor： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

IPC: H01L21/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/70 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A method of fabricating MOTFTs includes positioning opaque gate metal on a transparent substrate, depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Etch stop material is deposited on the semiconductor material. Photoresist defines an isolation area in the semiconductor material. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.

Abstract translation: 制造MOTFT的方法包括将不透明栅极金属定位在透明基板上，沉积覆盖栅极金属的栅介质材料和周围区域，以及在其上沉积金属氧化物半导体材料。 蚀刻停止材料沉积在半导体材料上。 光致抗蚀剂界定半导体材料中的隔离区。 从基板的后表面露出光致抗蚀剂，除去暴露的部分以使蚀刻停止材料未被覆盖，除了覆盖并与栅极金属对准的部分之外。 蚀刻半导体材料的未覆盖部分以隔离TFT。 使用光致抗蚀剂，选择性地蚀刻蚀刻停止层以留下覆盖并与栅极金属对准的部分并限定半导体材料中的沟道区域。 沉积和图案化导电材料以形成源区和漏区。

公开(公告)号：US09285615B2

公开(公告)日：2016-03-15

申请号：US13504042

申请日：2012-04-05

Applicant: Gang Yu

Inventor： Gang Yu

IPC: F21V7/04 ,  G02F1/1333

CPC classification number: G02F1/133308 ,  G02F2001/133314 ,  G02F2001/13332 ,  Y10T403/7045

Abstract: The invention discloses a structure for fixing frames and an LCD device. The structure for fixing frames includes a first frame and a second frame. The second frame is located inside of the first frame. Convex modules and countersinks are arranged in pairs on a contact surface between the first frame and the second frame. The convex modules are embedded into the countersinks for fixing the first frame and the second frame. The countersinks are blind holes. In the invention, because the frames are fixed by matching the countersinks with the convex modules and the countersinks are blind holes, no hollow structure is formed on the frame provided with the countersinks. Compared with the mounting structure having the through holes, the strength of the frames is significantly improved. When the two frames required to be installed are aligned and pressed, the convex modules is embedded into the countersinks for assembling the frames. This is a simple and efficient assembly method.

Abstract translation: 本发明公开了一种用于固定框架和LCD装置的结构。 用于固定框架的结构包括第一框架和第二框架。 第二帧位于第一帧的内部。 凸模块和埋头孔成对地布置在第一框架和第二框架之间的接触表面上。 凸模块嵌入到用于固定第一框架和第二框架的埋头孔中。 锪孔是盲孔。 在本发明中，由于通过将埋头孔与凸模块匹配来固定框架，并且埋头孔是盲孔，所以在设置有埋头孔的框架上不形成中空结构。 与具有通孔的安装结构相比，框架的强度显着提高。 当需要安装的两个框架对齐和按压时，凸模块嵌入到用于组装框架的埋头孔中。 这是一个简单而有效的装配方法。

公开(公告)号：US09176337B2

公开(公告)日：2015-11-03

申请号：US13575297

申请日：2012-06-05

Applicant: Yicheng Kuo ,  Shihhsiang Chen ,  Gang Yu ,  Gege Zhou ,  Jiaqiang Wang

Inventor： Yicheng Kuo ,  Shihhsiang Chen ,  Gang Yu ,  Gege Zhou ,  Jiaqiang Wang

IPC: F21V8/00 ,  G02F1/1333

CPC classification number: G02F1/133308 ,  G02B6/0088 ,  G02F2001/133317 ,  G02F2001/133328

Abstract: The present invention provides a backlight module, which includes a backplane, a backlight source arranged inside the backplane, a light guide plate arranged inside the backplane, an optic film assembly arranged on the light guide plate, and a split mold frame arranged inside the backplane. The split mold frame includes a plurality of spaced corner pieces respectively set on the optic film assembly. The corner pieces have a support surface that is distant from the optic film assembly for supporting thereon a liquid crystal display panel. The backlight module of the present invention uses an upper surface of a split mold frame to serve as a support surface for a liquid crystal display panel thereby enlarging the supporting area for the liquid crystal display pane, improving supporting stability and also effectively preventing the occurrence of light leakage, ensuring luminance of the backlight module, and enhancing optic grade.

Abstract translation: 本发明提供了一种背光模块，其包括背板，布置在背板内的背光源，布置在背板内的导光板，布置在导光板上的光学膜组件和布置在背板内部的分割模框 。 分割模框架包括分别设置在光学膜组件上的多个间隔开的角块。 角块具有远离用于支撑液晶显示面板的光学膜组件的支撑表面。 本发明的背光模块使用分割模框的上表面作为液晶显示面板的支撑面，从而扩大了液晶显示面板的支撑面积，提高了支撑稳定性，并且还有效地防止了 光泄漏，确保背光模块的亮度，并提高光学级。