公开(公告)号：US11289152B2

公开(公告)日：2022-03-29

申请号：US17077795

申请日：2020-10-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Ming-Liang Wei ,  Po-Kai Hsu ,  Hang-Ting Lue ,  Teng-Hao Yeh

IPC: G11C7/16 ,  G11C11/4091 ,  G06F9/38 ,  G11C11/4076 ,  G11C11/408 ,  G11C16/26 ,  G11C11/54 ,  G11C7/10

Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.

公开(公告)号：US10741247B1

公开(公告)日：2020-08-11

申请号：US16449158

申请日：2019-06-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/26 ,  G06F7/544 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A 3D memory array device includes blocks, bit lines, word lines, source lines (SL), complementary metal oxide semiconductors (COMS), and SL sensing amplifiers (SA). Each block includes NAND strings, and each memory cell in the NAND strings stores one or more weights. The bit lines are respectively coupled as signal inputs to string select lines in all blocks. The word lines are respectively coupled to the memory cells, and the word lines in the same layer are as a convolution layer to perform a convolution operation on the inputted signal. Different SL are coupled to all ground select lines in different blocks to independently collect a total current of the NAND strings in each block. The CMOS are disposed under the blocks and coupled to each source line for transferring the total current to each SL SA, and a multiply-accumulate result of each block is outputted via each SL SA.

公开(公告)号：US10403637B2

公开(公告)日：2019-09-03

申请号：US15410965

申请日：2017-01-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28

Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.

公开(公告)号：US10381094B2

公开(公告)日：2019-08-13

申请号：US15290376

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chen-Jun Wu ,  Chih-Chang Hsieh ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10

Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i−1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i−1).

公开(公告)号：US10276250B1

公开(公告)日：2019-04-30

申请号：US15818208

申请日：2017-11-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C16/12 ,  H01L27/11524 ,  H01L27/1157

Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.

公开(公告)号：US10211218B2

公开(公告)日：2019-02-19

申请号：US15344899

申请日：2016-11-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66

Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.

公开(公告)号：US09922989B2

公开(公告)日：2018-03-20

申请号：US15290179

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66666

Abstract: A memory device is provided. The memory device includes a bottom conductive line, a stacked structure, a side oxide layer, a dielectric layer and a side semiconductor layer. The stacked structure is disposed on the bottom conductive line, and includes a first semiconductor layer, a second semiconductor layer disposed above the first semiconductor layer, and a plurality of oxide layers alternately stacked with the first semiconductor layer and the second semiconductor layer. The side oxide layer is disposed on both side walls of the first conductive layer. The dielectric layer is disposed on the stacked structure. The side semiconductor layer is disposed on the dielectric layer.

公开(公告)号：US09397110B2

公开(公告)日：2016-07-19

申请号：US14284306

申请日：2014-05-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  G11C16/10 ,  G11C16/04

CPC classification number: H01L27/1157 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory device configurable for independent double gate cells, storing multiple bits per cell includes multilayer stacks of conductive strips configured as word lines. Active pillars are disposed between pairs of first and second stacks, each active pillar comprising a vertical channel structure, a charge storage layer and an insulating layer. The insulating layer in a frustum of an active pillar contacts a first arcuate edge of a first conductive strip in a layer of the first stack and a second arcuate edge of a second conductive strip in a same layer of the second stack. A plurality of insulating columns serve, with the active pillars, to divide the stacks of word lines into even and odd lines contacting opposing even and odd sides of each active pillar. The active pillar can be generally elliptical with a major axis parallel with the first and second conductive strips.

Abstract translation: 可独立的双栅极单元配置的存储器件，每个存储单元存储多个位包括配置为字线的导电条的多层堆叠。 活动柱设置在成对的第一和第二堆叠之间，每个活性柱包括垂直沟道结构，电荷存储层和绝缘层。 有源柱的截头锥体中的绝缘层与第二堆叠的同一层中的第一堆叠层中的第一导电条的第一弧形边缘和第二导电条的第二弧形边缘接触。 多个绝缘柱与活动柱一起用于将字线的叠层划分成偶数和奇数的线，从而接触每个有源柱的相对的偶数和奇数侧。 主动柱通常为椭圆形，长轴与第一和第二导电条平行。

公开(公告)号：US09379129B1

公开(公告)日：2016-06-28

申请号：US14685420

申请日：2015-04-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H01L27/105 ,  H01L27/115 ,  H01L23/528 ,  H01L21/265

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578

Abstract: A 3D array of memory cells with one or more blocks is described. The blocks include a plurality of layers. The layers in the plurality include semiconductor strips which extend from a semiconductor pad. The layers are disposed so that the semiconductor strips in the plurality of layers form a plurality of stacks of semiconductor strips and a stack of semiconductor pads. Also, a plurality of select gate structures are disposed over stacks of semiconductor strips in the plurality of stacks between the semiconductor pad and memory cells on the semiconductor strips. In addition, different ones of the plurality of select gate structures couple the semiconductor strips in different ones of the stacks of semiconductor strips to the semiconductor pads in the plurality of layers. Further, an assist gate structure is disposed over the plurality of stacks between the select gate structures and the stack of semiconductor pads.

Abstract translation: 描述具有一个或多个块的存储器单元的3D阵列。 这些块包括多个层。 多个层中的层包括从半导体衬垫延伸的半导体条。 这些层被设置成使得多个层中的半导体条形成多个半导体条的叠层和一叠半导体焊盘。 此外，多个选择栅极结构设置在半导体衬底和半导体条上的存储单元之间的多个堆叠中的半导体条的堆叠之上。 此外，多个选择栅极结构中的不同的选择栅极结构将半导体条的不同堆叠中的半导体条耦合到多个层中的半导体焊盘。 此外，辅助栅极结构设置在选择栅极结构和半导体焊盘堆之间的多个堆叠之上。

公开(公告)号：US09348748B2

公开(公告)日：2016-05-24

申请号：US14578820

申请日：2014-12-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Hsiang-Pang Li ,  Hang-Ting Lue ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G06F12/02 ,  G11C29/44 ,  G11C16/34

CPC classification number: G06F12/0246 ,  G06F12/00 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C16/3495 ,  G11C29/4401

Abstract: Technology is described that increases endurance of memory devices through heal leveling. Heal leveling is a lightweight solution to distribute healing cycles among memory blocks. Approaches described herein can accomplish heal leveling without introducing a large amount of overhead. Heal leveling significantly improves the access performance and the effective lifetime of memory blocks. By more evenly distributing the heal count it may not be necessary to directly apply wear leveling based on access counts of each block because each block will be more evenly accessed in the long run. Heal leveling may be performed by moving data that is seldom or never modified after creation, such as read-only files, to blocks having suffered the greatest number, or a high number, of healing cycles.

Abstract translation: 技术被描述为通过愈合平整来增加记忆装置的耐久性。 治疗矫正是一种轻量级的解决方案，可以在内存块之间分配愈合周期。 本文描述的方法可以在不引入大量开销的情况下完成愈合平整。 愈合程度显着提高了存储块的访问性能和有效寿命。 通过更均匀地分配治疗计数，可能不需要基于每个块的访问计数来直接应用磨损均衡，因为长期来看每个块将被更均匀地访问。 可以通过将创建后很少或从不修改的数据（例如只读文件）移动到遭受最大数量的块或大量愈合周期来执行愈合调平。