公开(公告)号：US20240112744A1

公开(公告)日：2024-04-04

申请号：US17957606

申请日：2022-09-30

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Wei Cao ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102

Abstract: The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.

公开(公告)号：US20240105265A1

公开(公告)日：2024-03-28

申请号：US17952846

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higashitani ,  Abhijith Prakash ,  Dengtao Zhao

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/3445 ,  H01L25/0657

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

公开(公告)号：US11935585B2

公开(公告)日：2024-03-19

申请号：US17509725

申请日：2021-10-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Arka Ganguly ,  Ohwon Kwon

IPC: G11C11/4096 ,  G06F3/06 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4096 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4074 ,  G11C11/4085

Abstract: An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

公开(公告)号：US20240071524A1

公开(公告)日：2024-02-29

申请号：US17895412

申请日：2022-08-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Henry Chin ,  Erika Penzo ,  Muhammad Masuduzzaman

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/14 ,  G11C16/3404

Abstract: Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.

公开(公告)号：US20240071482A1

公开(公告)日：2024-02-29

申请号：US17895304

申请日：2022-08-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Hua-Ling Cynthia Hsu

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459

Abstract: Technology is disclosed herein for mixed lockout verify. In a first programming phase, prior to a pre-determined data state completing verification, a no-lockout program verify is performed. After the pre-determined data state has completed verification, a lockout program verify is performed. The no-lockout verify may include charging all bit lines associated with the group to a sensing voltage to perform. The lockout verify may include selectively charging to the sensing voltage only bit lines associated with memory cells in the group to be verified. Bit lines associated with memory cells in the group that are not to be verified may be grounded to perform the lockout verify. The lockout verify saves considerable current and/or power. However, performing the lockout verify during the first programming phase may slow performance due to a need to scan the content in a remote set of data latches.

公开(公告)号：US20240055051A1

公开(公告)日：2024-02-15

申请号：US17888063

申请日：2022-08-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  YenLung Li ,  James Kai

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

公开(公告)号：US11894062B2

公开(公告)日：2024-02-06

申请号：US17398718

申请日：2021-08-10

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink ,  Shubhajit Mukherjee

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/28 ,  G11C16/34 ,  G11C16/3409 ,  G11C16/3445

Abstract: A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

公开(公告)号：US11862249B2

公开(公告)日：2024-01-02

申请号：US17527747

申请日：2021-11-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Fanqi Wu ,  Jiacen Guo ,  Jiahui Yuan

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  G11C16/24 ,  H10B43/27 ,  G11C11/56 ,  H01L25/065 ,  H10B43/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3427 ,  H10B43/27 ,  G11C11/5671 ,  H01L25/0657 ,  H01L2225/06562 ,  H10B43/10

Abstract: In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.

公开(公告)号：US20230410922A1

公开(公告)日：2023-12-21

申请号：US17841343

申请日：2022-06-15

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages targeted for each of the memory cells during a program-verify portion of a program operation. The control means is also configured to trim the program verify voltages for each of the data states for a grouping of the memory cells based on quantities of the memory cells having the threshold voltage crossing over between the data states in crossovers in a verify level trimming process.

公开(公告)号：US20230410912A1

公开(公告)日：2023-12-21

申请号：US17841160

申请日：2022-06-15

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory apparatus also includes a control means coupled to the drain-side select gate transistor of each of the plurality of memory holes. The control means is configured to select the transistor threshold voltage of the drain-side select gate transistors as a stable transistor threshold voltage for a grouping of the memory cells to minimize shifting of the transistor threshold voltage following a plurality of read operations of the memory cells. The control means is also configured to program the transistor threshold voltage of the drain-side select gate transistor of the plurality of memory holes associated with the grouping of the memory cells to the stable transistor threshold voltage.