公开(公告)号：US20200098750A1

公开(公告)日：2020-03-26

申请号：US16362864

申请日：2019-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Kuo-Cheng Ching

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

公开(公告)号：US20200006577A1

公开(公告)日：2020-01-02

申请号：US16358314

申请日：2019-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/423

Abstract: A method of fabricating a semiconductor device includes forming a fin extruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged; removing a portion of the sacrificial layers from a channel region of the fin; depositing a spacer material in areas from which the portion of the sacrificial layers have been removed; selectively removing a portion of the spacer material, thereby exposing the channel layers in the channel region of the fin, wherein other portions of the spacer material remain as a spacer feature; and forming a gate structure engaging the exposed channel layers.

公开(公告)号：US10510873B2

公开(公告)日：2019-12-17

申请号：US15635337

申请日：2017-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

公开(公告)号：US10483378B2

公开(公告)日：2019-11-19

申请号：US15800287

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238

Abstract: A semiconductor structure includes a substrate; a first semiconductor fin extending upwardly from the substrate; an isolation structure over the substrate and on sidewalls of the first semiconductor fin; a first epitaxial feature over the first semiconductor fin; a dielectric fin partially embedded in the isolation structure and projecting upwardly above the isolation structure; and first and second spacer features over the isolation structure. The first spacer feature is laterally between the first epitaxial feature and the dielectric fin. The first epitaxial feature is laterally between the first and second spacer features. Methods of forming the same are also disclosed.

公开(公告)号：US10361280B2

公开(公告)日：2019-07-23

申请号：US15857196

申请日：2017-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/45 ,  H01L21/28 ,  H01L29/423

Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.

公开(公告)号：US20190067444A1

公开(公告)日：2019-02-28

申请号：US15691437

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/6681 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

公开(公告)号：US10181426B1

公开(公告)日：2019-01-15

申请号：US15800959

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively.

公开(公告)号：US10157751B1

公开(公告)日：2018-12-18

申请号：US15794262

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hao Chang ,  Chao-Hsien Huang ,  Wen-Ting Lan ,  Shi-Ning Ju ,  Li-Te Lin ,  Kuo-Cheng Ching

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device, including forming a first hard mask strip, a second hard mask strip, and a dummy structure over a substrate, in which the dummy structure is formed between and in contact with the first hard mask strip and the second hard mask strip; forming a hard mask layer over the first hard mask strip, the dummy structure, and the second hard mask strip; patterning the hard mask layer to form an opening exposing the first hard mask strip and the dummy structure, and partially exposing the second hard mask strip; and performing an etching process to remove the first hard mask strip and form a recess in the second hard mask strip, in which the performing the etching process includes forming a polymer in the recess.

公开(公告)号：US20170372969A1

公开(公告)日：2017-12-28

申请号：US15261302

申请日：2016-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02247 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02634 ,  H01L21/76237 ,  H01L21/823481 ,  H01L29/7851

Abstract: A FinFET includes a semiconductor layer having a fin structure that protrudes out of the semiconductor layer. The fin structure includes a first segment and a second segment disposed over the first segment. A dielectric layer is disposed over the semiconductor layer. The first segment of the fin structure is surrounded by the dielectric layer. A metal layer is disposed over the dielectric layer. The second segment of the fin structure is surrounded by the metal layer. The dielectric layer has a greater nitrogen content than the metal layer. The first segment of the fin structure also has a first side surface that is rougher than a second side surface of the second segment of the fin structure.

公开(公告)号：US20170345936A1

公开(公告)日：2017-11-30

申请号：US15235233

申请日：2016-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Ching-Wei Tsai ,  Ying-Keung Leung ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.