公开(公告)号：US20050086276A1

公开(公告)日：2005-04-21

申请号：US10935193

申请日：2004-09-08

申请人： Takashi Masuno ,  Tatsuro Juri

发明人： Takashi Masuno ,  Tatsuro Juri

IPC分类号： G06F9/38 ,  G06F7/00 ,  G06F7/544 ,  G06F7/57 ,  G06F15/80 ,  G06F17/10 ,  H04N1/41 ,  H04N7/24 ,  H04N19/00 ,  H04N19/436 ,  H04N19/533 ,  H04N19/625 ,  H04N19/80

CPC分类号： G06F7/57 ,  G06F7/544 ,  G06F2207/5442 ,  H04N19/42 ,  H04N19/43 ,  H04N19/60 ,  H04N19/61

摘要： The arithmetic processing apparatus of the present invention is an arithmetic processing apparatus that can be reconfigured in accordance with a processing mode and has a plurality of arranged unit arithmetic circuits. Each unit arithmetic circuit includes at least one input terminal, at least one output terminal, a first register which holds data, an adder which calculates a sum of two pieces of data, a second register which holds data, a bit shifter which shifts data left or right, a subtractor which calculates a difference between two pieces of data, an absolute value calculating unit which calculates an absolute value of data, and a path setting unit which sets a path according to the processing mode connecting among these circuit elements.

摘要翻译： 本发明的算术处理装置是可以根据处理模式重新配置并具有多个排列的单元运算电路的运算处理装置。 每个单元运算电路包括至少一个输入端子，至少一个输出端子，保存数据的第一寄存器，计算两条数据之和的加法器，保存数据的第二寄存器，向左移位数据的位移位器 或右，计算两个数据之间的差的减法器，计算数据的绝对值的绝对值计算单元和根据连接在这些电路元件之间的处理模式设置路径的路径设置单元。

公开(公告)号：US06744928B1

公开(公告)日：2004-06-01

申请号：US09380794

申请日：1999-09-09

申请人： Tatsuro Juri ,  Tadashi Ono

发明人： Tatsuro Juri ,  Tadashi Ono

IPC分类号： G06K936

CPC分类号： H04N19/88 ,  H04N19/124 ,  H04N19/126 ,  H04N19/13 ,  H04N19/132 ,  H04N19/14 ,  H04N19/176 ,  H04N19/30 ,  H04N19/423 ,  H04N19/60 ,  H04N19/61 ,  H04N19/90 ,  H04N19/91

摘要： The present invention includes methods and apparatus for attaining high speed coding and decoding. A first method decreases the number of memory access times by performing signal format conversion, orthogonal transform and continuous variable-length coding with predetermined small areas in a frame used as units. A second method omits orthogonal transform computation by using orthogonal transform coefficients to shorten the processing time. A third method uses additions and subtractions for orthogonal transform thereby decreasing the number of registers used and reducing the number of memory access times. The present invention further includes a decoding method for variable-length decoding wherein table size is not made larger because the number of table access times per code word is set to a maximum of 2, and plural code words are decoded by one tale access operation to attain high-speed decoding.

摘要翻译： 本发明包括用于实现高速编码和解码的方法和装置。 第一种方法是通过执行信号格式转换，正交变换和连续可变长度编码来减少存储器访问次数，并且使用作为单位的帧中的预定小区域进行连续可变长度编码。 第二种方法通过使用正交变换系数来省略正交变换计算，以缩短处理时间。 第三种方法使用加法和减法进行正交变换，从而减少使用的寄存器数量并减少存储器访问次数。 本发明还包括一种用于可变长度解码的解码方法，其中由于每个码字的表访问次数被设置为最大值2，所以不增大表的大小，并且通过一个传播操作将多个码字解码为 达到高速解码。

公开(公告)号：US06049770A

公开(公告)日：2000-04-11

申请号：US186

申请日：1998-05-29

申请人： Junji Yoshida ,  Akira Iketani ,  Chiyoko Matsumi ,  Tatsuro Juri

发明人： Junji Yoshida ,  Akira Iketani ,  Chiyoko Matsumi ,  Tatsuro Juri

IPC分类号： H04N5/44 ,  H04N5/60 ,  H04N5/91 ,  H04N7/26 ,  H04N7/52 ,  G10L9/00

CPC分类号： H04N21/2368 ,  H04N19/85 ,  H04N21/4341 ,  H04N5/4401 ,  H04N5/602 ,  H04N5/91

摘要： A video and voice signal processing apparatus is provided. The apparatus includes a signal receiving circuit for receiving an input signal containing a plurality of frames, each frame having an encoded voice signal block and an encoded video signal block. The signal receiving circuit separates the encoded voice signal block from the encoded video signal block in each frame. A voice signal processor converts the encoded voice signal block into a voice signal. Also included is a video extracting circuit which decimates a plurality of encoded video signal blocks and extracts one of the encoded video signal blocks as a representative video signal. A video signal processor converts the representative video signal into a video signal.

摘要翻译： PCT No.PCT / JP97 / 01641 Sec。 371日期1998年5月23日 102（e）日期1998年5月23日PCT提交1997年5月15日PCT公布。 WO97 / 44953 PCT出版物 日期：1997年11月27日提供了视频和语音信号处理装置。 该装置包括用于接收包含多个帧的输入信号的信号接收电路，每个帧具有编码语音信号块和编码视频信号块。 信号接收电路将编码的声音信号块与编码视频信号块在每帧中分离。 语音信号处理器将编码的语音信号块转换成语音信号。 还包括一个视频提取电路，它对多个编码的视频信号块进行抽取，并将一个编码的视频信号块作为代表性视频信号提取。 视频信号处理器将代表性视频信号转换为视频信号。

公开(公告)号：US5867626A

公开(公告)日：1999-02-02

申请号：US884394

申请日：1997-06-27

申请人： Yasunori Kawakami ,  Tatsuro Juri

发明人： Yasunori Kawakami ,  Tatsuro Juri

IPC分类号： H04N3/20 ,  H04N5/765 ,  H04N5/92 ,  H04N5/926 ,  H04N7/24 ,  H04N7/52 ,  H04N7/56 ,  H04N9/00 ,  H04N11/00 ,  H04N7/13

CPC分类号： H04N21/4402 ,  H04N21/4341 ,  H04N21/43622 ,  H04N5/765 ,  H04N5/9208 ,  H04N5/9268 ,  H04N7/56

摘要： In a data transmission apparatus for transmitting digital video and audio data, a block forming circuit forms a plurality of data blocks of transmission data composed of at least one of digital video data, digital audio data, and digital auxiliary data related to the digital video data and the digital audio data. Thereafter, a grouping circuit groups a plurality of data blocks outputted from the block forming circuit so as to form transmission group data of one transmission unit block having a time length of approximately one three-hundredth second, and then transmits the transmission group data. Further, a classifying circuit preferably classifies the transmission group data into a plurality of sections, by adding section identification data to each transmission group data.

公开(公告)号：US5691819A

公开(公告)日：1997-11-25

申请号：US197490

申请日：1994-02-16

申请人： Hirofumi Uchida ,  Tatsuro Juri

发明人： Hirofumi Uchida ,  Tatsuro Juri

IPC分类号： H03M7/30 ,  G06T9/00 ,  H04N5/783 ,  H04N5/92 ,  H04N5/935 ,  H04N7/16 ,  H04N9/804 ,  H04N19/13 ,  H04N19/146 ,  H04N19/174 ,  H04N19/196 ,  H04N19/42 ,  H04N19/423 ,  H04N19/426 ,  H04N19/60 ,  H04N19/65 ,  H04N19/70 ,  H04N19/85 ,  H04N19/88 ,  H04N19/89 ,  H04N19/91 ,  H04N21/433 ,  H04N9/79

CPC分类号： H04N5/935 ,  H04N9/8047 ,  H04N5/783

摘要： A video image of one frame is divided into a plurality of super blocks, and each super block comprises a plurality of macro blocks. A video segment comprising five macro blocks taken out from five super blocks located apart from each other on the video image, and data compression operation is applied in the video segment. After data compression, the macro blocks in the video segment are rearranged in the original order, and are formed to corresponding SYNC block data to record on a magnetic tape.

摘要翻译： 一帧的视频图像被分成多个超块，每个超块包括多个宏块。 视频片段包括从视频图像上彼此分开的五个超级块中取出的五个宏块，以及数据压缩操作。 在数据压缩之后，视频段中的宏块以原始顺序重新排列，并形成相应的SYNC块数据，以便在磁带上进行记录。

公开(公告)号：US5543937A

公开(公告)日：1996-08-06

申请号：US235956

申请日：1994-05-02

申请人： Shinji Hamai ,  Akira Iketani ,  Chiyoko Matsumi ,  Tatsuro Juri ,  Masazumi Yamada ,  Yasunori Kawakami ,  Yuuzou Murakami

发明人： Shinji Hamai ,  Akira Iketani ,  Chiyoko Matsumi ,  Tatsuro Juri ,  Masazumi Yamada ,  Yasunori Kawakami ,  Yuuzou Murakami

IPC分类号： H04N5/783 ,  H04N5/926 ,  H04N5/93 ,  H04N5/945

CPC分类号： H04N5/945 ,  H04N5/9268 ,  H04N5/93 ,  H04N5/783

摘要： An apparatus serving as a digital videocassette recorder (VCR) for recording analog video and audio signals as digital signals. The apparatus serves also as a digital data storage drive. The digital VCR and the storage drive share common circuitry and a common magnetic recording medium. This reduces the cost and enhances the efficiency at which tracks are used. The apparatus has a large storage capacity. The apparatus divides input digital data into two parts and performs error correction encoding for each of these two data parts to form sync blocks. These sync blocks are recorded in an audio signal recording area and a video signal recording area, respectively, on the recording medium. Error correction codes used during reading of digital data are the same as those used during recording of video and audio signals. The same track structure and the same sync block structure are used for these two modes of operation.

摘要翻译： 一种用作数字录像机（VCR）的装置，用于将模拟视频和音频信号作为数字信号进行记录。 该装置还用作数字数据存储驱动器。 数字VCR和存储驱动器共享公共电路和公共磁记录介质。 这降低了成本并提高了使用轨道的效率。 该设备具有大的存储容量。 该装置将输入数字数据分成两部分，并对这两个数据部分中的每一个执行纠错编码以形成同步块。 这些同步块分别记录在记录介质上的音频信号记录区和视频信号记录区中。 在数字数据读取期间使用的纠错码与记录视频和音频信号时使用的纠错码相同。 对于这两种操作模式，使用相同的轨道结构和相同的同步块结构。

公开(公告)号：US5317457A

公开(公告)日：1994-05-31

申请号：US741048

申请日：1991-08-06

申请人： Chiyoko Matsumi ,  Akira Iketani ,  Akifumi Ide ,  Tatsuro Juri

发明人： Chiyoko Matsumi ,  Akira Iketani ,  Akifumi Ide ,  Tatsuro Juri

IPC分类号： G11B5/008 ,  G11B5/584 ,  G11B5/588 ,  G11B15/46 ,  G11B15/467 ,  G11B20/12 ,  G11B20/14 ,  G11B21/10 ,  G11B5/09

CPC分类号： G11B5/584 ,  G11B15/463 ,  G11B20/1208 ,  G11B20/1426 ,  G11B21/103 ,  G11B5/0086 ,  G11B2020/10537 ,  G11B21/10 ,  G11B2220/90 ,  G11B5/588

摘要： A specific section provided in a track is set in a DC free state, and during reproducing, accurate tracking is conducted on the basis of the crosstalk from the pilot tone superposed in the adjacent tracks in this DC free section. Alternatively, a pilot tone is generated only in a specific section provided in the track, and when reproducing, accurate tracking is effected on the basis of the crosstalk of the pilot tone in the tracks adjacent to this section. As a result, the redundancy required for tracking is notably reduced.

摘要翻译： 设置在轨道中的特定部分被设置为无DC状态，并且在再现期间，基于来自叠加在该DC自由部分中的相邻轨道中的导频音的串扰进行精确跟踪。 或者，仅在轨道中提供的特定部分中产生导频音，并且当再现时，基于与该部分相邻的轨道中的导频音的串扰进行精确跟踪。 结果，跟踪所需的冗余显着降低。

公开(公告)号：US5193010A

公开(公告)日：1993-03-09

申请号：US574288

申请日：1990-08-28

申请人： Tatsuro Juri ,  Chiyoko Matsumi ,  Shinya Kadono ,  Hideki Ohtaka

发明人： Tatsuro Juri ,  Chiyoko Matsumi ,  Shinya Kadono ,  Hideki Ohtaka

IPC分类号： G11B20/00 ,  G11B20/18 ,  G11B27/032 ,  H04N5/926 ,  H04N5/945 ,  H04N19/89 ,  H04N19/895

CPC分类号： G11B27/032 ,  G11B20/00086 ,  G11B20/1809 ,  H04N19/142 ,  H04N19/179 ,  H04N19/87 ,  H04N19/89 ,  H04N19/895 ,  H04N5/926 ,  H04N5/945 ,  G11B2220/90 ,  H04N19/60 ,  H04N19/65

摘要： In recording and reproducing the digital video signals by bit rate reduction, if they are copied while being subjected to bit rate reduction, no accumulation of distortions in orthogonal transformation or bit rate reduction occurs, and moreover, copying can be done at a low data rate. On the other hand, in case of dividing the data into blocks in each page and transmitting or recording and reproducing the data by block, by concealing the error by the data having the strongest correlation out of the data located in the pages before and after the block in which error has been detected, no degradation in image quality is induced even when the scene changes between pages. Further, at the same time, by detecting the previous concealment information, if there exists a block which was previously concealed in the block in which error has at present been detected, then the data can be fully reproduced by utilizing it, and degradation in image quality can be reduced to a minimum. Also, if degradation in image quality is reduced to a minimum, then the degradation in image quality in the case of repeated copying is reduced to a minimum.

公开(公告)号：US4868654A

公开(公告)日：1989-09-19

申请号：US161928

申请日：1988-02-29

申请人： Tatsuro Juri ,  Minoru Etoh

发明人： Tatsuro Juri ,  Minoru Etoh

IPC分类号： H04N19/00 ,  H04N19/132 ,  H04N19/137 ,  H04N19/182 ,  H04N19/196 ,  H04N19/46 ,  H04N19/463 ,  H04N19/59 ,  H04N19/70 ,  H04N19/80

CPC分类号： H04N19/587

摘要： A sub-Nyguist sampling encoder and decoder has a plurality of interpolators provided in an encoder and corresponding plural interpolators provided in a decoder. Information indicating which interpolator can be used to minimize the interpolation error is superimposed on a value of a non-thinned-out pixel and transmitted from the encoder to the decoder, and the decoder receiving the information is permitted to always perform optimum interpolation. The interpolation information is superimposed on the least significant bit of the value of the non-thinned-out pixel, with the view of effecting the superimposition without increasing the amount of transmission data and without degrading quality of the video signal.