公开(公告)号：US5193010A

公开(公告)日：1993-03-09

申请号：US574288

申请日：1990-08-28

申请人： Tatsuro Juri ,  Chiyoko Matsumi ,  Shinya Kadono ,  Hideki Ohtaka

发明人： Tatsuro Juri ,  Chiyoko Matsumi ,  Shinya Kadono ,  Hideki Ohtaka

IPC分类号： G11B20/00 ,  G11B20/18 ,  G11B27/032 ,  H04N5/926 ,  H04N5/945 ,  H04N19/89 ,  H04N19/895

CPC分类号： G11B27/032 ,  G11B20/00086 ,  G11B20/1809 ,  H04N19/142 ,  H04N19/179 ,  H04N19/87 ,  H04N19/89 ,  H04N19/895 ,  H04N5/926 ,  H04N5/945 ,  G11B2220/90 ,  H04N19/60 ,  H04N19/65

摘要： In recording and reproducing the digital video signals by bit rate reduction, if they are copied while being subjected to bit rate reduction, no accumulation of distortions in orthogonal transformation or bit rate reduction occurs, and moreover, copying can be done at a low data rate. On the other hand, in case of dividing the data into blocks in each page and transmitting or recording and reproducing the data by block, by concealing the error by the data having the strongest correlation out of the data located in the pages before and after the block in which error has been detected, no degradation in image quality is induced even when the scene changes between pages. Further, at the same time, by detecting the previous concealment information, if there exists a block which was previously concealed in the block in which error has at present been detected, then the data can be fully reproduced by utilizing it, and degradation in image quality can be reduced to a minimum. Also, if degradation in image quality is reduced to a minimum, then the degradation in image quality in the case of repeated copying is reduced to a minimum.

公开(公告)号：US5329475A

公开(公告)日：1994-07-12

申请号：US979668

申请日：1992-11-20

申请人： Tatsuro Juri ,  Shinya Kadono

发明人： Tatsuro Juri ,  Shinya Kadono

IPC分类号： G06F7/38 ,  G06F7/48 ,  H03M7/30 ,  H04N1/41 ,  H04N11/04 ,  H04N19/115 ,  H04N19/132 ,  H04N19/136 ,  H04N19/60 ,  H04N19/85 ,  H04N19/91

CPC分类号： H03M7/30 ,  G06F7/48 ,  G06F7/49952 ,  G06F7/49963

摘要： A data round-off device receives a digital input signal of m-bit form (m is an integer) which has arithmetically been processed by addition, subtraction, multiplication, and division by an orthogonal transformer or predictive encoder is summed, if it is positive, with a value of 2.sup.(n-1) -1 (n is a natural number smaller than m) and if negative, with a value of 2.sup.(n-1) and the higher (m-n) bits of a resultant sum signal are delivered as the output of the data round-off device. Preferably, it is used for control of the number of bits if there is a difference in the number of bits between the data output of an orthogonal transformer and the data input of an encoder for encoding the data output of the orthogonal transformer.

摘要翻译： 数据舍入装置接收通过正交变换器或预测编码器的加法，减法，乘法和除法进行算术处理的m位形式（m为整数）的数字输入信号，如果为正， ，其值为2（n-1）-1（n是小于m的自然数），如果为负，则所得到的和信号的值为2（n-1）和高（mn） 作为数据舍入装置的输出。 优选地，如果正交变换器的数据输出与用于编码正交变换器的数据输出的编码器的数据输入之间的位数差异，则用于控制位数。

公开(公告)号：US5343501A

公开(公告)日：1994-08-30

申请号：US836660

申请日：1992-02-18

申请人： Shinya Kadono ,  Masakazu Nishino ,  Tatsuro Juri ,  Hiroshi Horikane ,  Iwao Hidaka

发明人： Shinya Kadono ,  Masakazu Nishino ,  Tatsuro Juri ,  Hiroshi Horikane ,  Iwao Hidaka

IPC分类号： G06F17/14 ,  H04L27/06 ,  G06F7/38

CPC分类号： G06F17/147

摘要： In an apparatus for executing an algorithm for realizing an orthogonal transform operation such as the 8 points fast cosine transform, by operating on successive sets of data values of a digital signal such as a digital video signal in such applications as high efficiency coding of a digital video signal, a plurality of multiplication operations that are executed during processing of each set of data values are executed sequentially by time division multiplex operation of a single multiplier (32) which is capable of executing a multiplication operation within one sample period of the digital signal, with input and output data values being transferred by selector units (11, 33, 41) between the multiplier and other sections of the apparatus at appropriate times during processing of each set of the input digital signal values. The scale of hardware required for the apparatus is thereby reduced by comparison with an apparatus which employs a plurality of separate multipliers.

摘要翻译： 在用于执行诸如8点快速余弦变换的正交变换操作的算法的装置中，通过在诸如数字视频信号的数字信号的数据信号的连续集合上进行操作，例如在数字 视频信号，在每个数据值集合的处理期间执行的多个乘法运算通过在数字信号的一个采样周期内能够执行乘法运算的单个乘法器（32）的时分多路复用操作来顺序执行 ，其中输入和输出数据值由选择器单元（11,33,41）在设备的乘法器和其它部分之间的适当时间在每组输入数字信号值的处理期间传送。 与使用多个单独的乘法器的装置相比，装置所需的硬件规模由此减少。

公开(公告)号：US5218563A

公开(公告)日：1993-06-08

申请号：US736056

申请日：1991-07-26

申请人： Tatsuro Juri ,  Shinya Kadono

发明人： Tatsuro Juri ,  Shinya Kadono

IPC分类号： G06F7/38 ,  G06F7/48 ,  H03M7/30 ,  H04N1/41 ,  H04N11/04 ,  H04N19/115 ,  H04N19/132 ,  H04N19/136 ,  H04N19/60 ,  H04N19/85 ,  H04N19/91

CPC分类号： H03M7/30 ,  G06F7/48 ,  G06F7/49952 ,  G06F7/49963

摘要： A data round-off device receives a digital input signal of m-bit form (m is an integer) which has arithmetically been processed by addition, subtraction, multiplication, and division by an orthogonal transformer or predictive encoder is summed, if it is positive, with a value of 2.sup.(n-1) -1 (n is a natural number smaller than m) and if negative, with a value of 2.sup.(n-1) and the higher (m-n) bits of a resultant sum signal are delivered as the output of the data round-off device. Preferably, it is used for control of the number of bits if there is a difference in the number of bits between the data output of an orthogonal transformer and the data input of an encoder for encoding the data output of the orthogonal transformer.

公开(公告)号：US5196930A

公开(公告)日：1993-03-23

申请号：US731311

申请日：1991-07-17

申请人： Shinya Kadono ,  Tatsuro Juri

发明人： Shinya Kadono ,  Tatsuro Juri

IPC分类号： G06F17/14 ,  H04N7/26

CPC分类号： G06F17/147 ,  H04N19/112 ,  H04N19/98 ,  H04N19/30

摘要： In a high efficiency coding apparatus for performing plural different types of orthogonal transformation, by reordering the signals after orthogonal transformation and transforming into signals of same statistic characteristics, distortion of coding efficiency due to mismatching of the characteristics of coding device is reduced even if the output of the orthogonally transformed signal is coded by one fixed coding device.

公开(公告)号：US5117381A

公开(公告)日：1992-05-26

申请号：US739106

申请日：1991-08-01

申请人： Tatsuro Juri ,  Shinya Kadono

发明人： Tatsuro Juri ,  Shinya Kadono

IPC分类号： G06F17/14 ,  H04N7/26 ,  H04N7/30

CPC分类号： G06F17/147 ,  H04N19/126 ,  H04N19/60 ,  H04N19/124

摘要： Eight point Discrete Cosine Transform (DCT) and eight point DCT can be calculated by not more than 8 multiplications by performing a given weighting for each component of orthogonal transformation of DCT and inverse DCT. An orthogonal transformation apparatus can be implemented by one multiplication unit, one addition unit or substraction unit, three butterfly operation units, several resequence units, delay units and selector unit by using one multiplication unit which is capable of one multiplication per one sample on a time-sharing basis.

公开(公告)号：US5140323A

公开(公告)日：1992-08-18

申请号：US741049

申请日：1991-08-06

申请人： Shinya Kadono ,  Tatsuro Juri

发明人： Shinya Kadono ,  Tatsuro Juri

IPC分类号： H04N19/60 ,  G06F17/14 ,  G06T9/00 ,  H03M7/14 ,  H03M7/16 ,  H03M7/30 ,  H04N1/41 ,  H04N11/04 ,  H04N19/44 ,  H04N19/85

CPC分类号： H03M7/16 ,  H03M7/14

摘要： As an orthogonally transformed signal carries a value adjacent to zero, the output of an orthogonal transformer is coupled in series to a fixed length code encoder for converting the orthogonally transformed signal into a fixed length code signal which exhibits less bit inversion between positive and negative signals near zero. The orthogonal transformer and the fixed length code encoder constitute in combination an orthogonal transformer device.

公开(公告)号：US08964839B2

公开(公告)日：2015-02-24

申请号：US13486358

申请日：2012-06-01

申请人： Satoshi Kondo ,  Shinya Kadono ,  Makoto Hagai

发明人： Satoshi Kondo ,  Shinya Kadono ,  Makoto Hagai

IPC分类号： H04N19/00 ,  H04N19/423 ,  H04N19/51 ,  H04N19/583 ,  H04N19/16 ,  H04N19/44 ,  H04N19/70 ,  H04N19/105 ,  H04N19/107 ,  H04N19/137 ,  H04N19/172 ,  H04N19/176 ,  H04N19/127 ,  H04N19/61 ,  H04N19/136 ,  H04N19/43 ,  H04N19/103 ,  H04N19/577 ,  H04N19/46 ,  H04N19/157

CPC分类号： H04N19/00 ,  H04N19/103 ,  H04N19/105 ,  H04N19/107 ,  H04N19/127 ,  H04N19/136 ,  H04N19/137 ,  H04N19/157 ,  H04N19/159 ,  H04N19/16 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/43 ,  H04N19/44 ,  H04N19/46 ,  H04N19/50 ,  H04N19/51 ,  H04N19/573 ,  H04N19/577 ,  H04N19/58 ,  H04N19/61 ,  H04N19/70

摘要： A moving picture coding apparatus for performing inter-picture predictive coding for pictures constituting a moving picture is provided with a coding unit for performing predictive error coding for image data; a decoding unit for performing predictive error decoding for an output from the coding unit; a reference picture memory for holding output data from the decoding unit; and a motion vector detection unit for detecting motion vectors on the basis of the decoded image data stored in the memory. When coding a B picture as a target picture, information indicating whether or not the target picture should be used as a reference picture when coding another picture is added as header information. Therefore, in a decoding apparatus for decoding a bit stream Bs outputted from the moving picture coding apparatus, management of a memory for holding the reference picture can be facilitated on the basis of the header information.

公开(公告)号：US08948265B2

公开(公告)日：2015-02-03

申请号：US13372885

申请日：2012-02-14

申请人： Shinya Kadono ,  Satoshi Kondo ,  Makoto Hagai ,  Kiyofumi Abe

发明人： Shinya Kadono ,  Satoshi Kondo ,  Makoto Hagai ,  Kiyofumi Abe

IPC分类号： H04B1/66 ,  H04N19/51 ,  G06F1/03 ,  H04N21/2743 ,  H04N19/583 ,  H04N19/61 ,  H04N19/43 ,  H04N19/577 ,  H04N19/503

CPC分类号： H04N19/52 ,  G06F1/03 ,  G06F2101/12 ,  H04N19/105 ,  H04N19/124 ,  H04N19/172 ,  H04N19/176 ,  H04N19/30 ,  H04N19/43 ,  H04N19/503 ,  H04N19/51 ,  H04N19/513 ,  H04N19/577 ,  H04N19/587 ,  H04N19/61 ,  H04N19/625 ,  H04N21/2743

摘要： A motion vector derivation unit includes a comparison unit for comparing a parameter TR1 for a reference vector with a predetermined value to determine whether it exceeds the predetermined value or not; a switching unit for switching selection between the maximum value of a pre-stored parameter TR and the parameter TR1 according to the comparison result by the comparison unit; a multiplier parameter table (for multipliers); and a multiplier parameter table (for divisors) for associating the parameter TR1 with a value approximate to the inverse value (1/TR1) of this parameter TR1.

摘要翻译： 运动矢量导出单元包括比较单元，用于将参考矢量的参数TR1与预定值进行比较，以确定其是否超过预定值; 切换单元，用于根据比较单元的比较结果切换预存储参数TR的最大值与参数TR1之间的选择; 乘数参数表（用于乘数）; 以及用于将参数TR1与接近该参数TR1的反相值（1 / TR1）的值相关联的乘数参数表（用于除数）。

公开(公告)号：US08704868B2

公开(公告)日：2014-04-22

申请号：US13125681

申请日：2010-08-11

申请人： Hidekatsu Ozeki ,  Shinya Kadono

发明人： Hidekatsu Ozeki ,  Shinya Kadono

IPC分类号： H04N7/14

CPC分类号： H04N7/15 ,  H04M3/54 ,  H04M3/567 ,  H04N7/147

摘要： To provide a video conferencing system that a user can continue to use even when the user leaves for a different location. The video conferencing system includes: a takeover information generation unit which generates takeover information including configuration information on a screen layout used in a video conference held between a first video conferencing apparatus and a second video conferencing apparatus; a sending unit which sends the takeover information; a receiving unit which receives the takeover information; and a takeover setting unit which sets a screen layout of the third video conferencing apparatus using the takeover information received by the receiving unit, so that the third video conferencing apparatus takes over the screen layout and has the video conference with the second video conferencing apparatus after participation of the third video conferencing apparatus in the video conference is approved.

摘要翻译： 提供即使用户离开不同位置的用户也可以继续使用的视频会议系统。 视频会议系统包括：接管信息生成单元，其生成包含在第一视频会议装置和第二视频会议装置之间保持的视频会议中使用的屏幕布局的配置信息的接收信息; 发送接收信息的发送单元; 接收单元，其接收所述收购信息; 以及接管设定单元，其使用由所述接收单元接收的所述接管信息来设定所述第三视频会议设备的屏幕布局，使得所述第三视频会议设备接管所述屏幕布局，并且在所述第二视频会议设备之后进行与所述第二视频会议设备的视频会议， 视频会议中第三台视频会议设备的参与获得通过。