公开(公告)号：US20240431118A1

公开(公告)日：2024-12-26

申请号：US18822490

申请日：2024-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H10B53/30

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

公开(公告)号：US20240222355A1

公开(公告)日：2024-07-04

申请号：US18105888

申请日：2023-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Peng-Hsiu Chen ,  Su-Ming Hsieh ,  Chun-Hsien Lin

IPC: H01L27/02 ,  H01L27/085 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0207 ,  H01L27/085 ,  H01L29/0692 ,  H01L29/66462 ,  H01L29/7786

Abstract: The invention provides a layout pattern of a semiconductor cell, which comprises a substrate with a first L-shaped MESA region and a second L-shaped MESA region, wherein the shapes of the first L-shaped MESA region and the second L-shaped MESA region are mutually inverted by 180 degrees, a first high electron mobility transistor (HEMT) and a second high electron mobility transistor are located on the first L-shaped MESA region, and a third high electron mobility transistor and a fourth high electron mobility transistor are located on the second L-shaped MESA region.

公开(公告)号：US20240074329A1

公开(公告)日：2024-02-29

申请号：US18505074

申请日：2023-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Sheng-Yuan Hsueh

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/20 ,  H10B61/22 ,  H10N50/01 ,  H10N50/85

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

公开(公告)号：US20240006405A1

公开(公告)日：2024-01-04

申请号：US17875430

申请日：2022-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Lin ,  Chien-Hung Chen ,  Ruei-Yau Chen

IPC: H01L27/02 ,  H01L27/118 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L21/823481 ,  H01L2027/11831

Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

公开(公告)号：US20230378166A1

公开(公告)日：2023-11-23

申请号：US17844088

申请日：2022-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/7851 ,  H01L29/66795

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a resistor region, forming a first gate structure on the resistor region, forming a first interlayer dielectric (ILD) layer around the first gate structure, transforming the first gate structure into a first metal gate having a gate electrode on the substrate and a hard mask on the gate electrode, and then forming a resistor on the first metal gate.

公开(公告)号：US20230335622A1

公开(公告)日：2023-10-19

申请号：US18213903

申请日：2023-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L21/02054 ,  H01L21/02052 ,  H01L29/517

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

公开(公告)号：US11791412B2

公开(公告)日：2023-10-17

申请号：US17706553

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shou-Wan Huang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L27/08 ,  H01L27/088 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0688 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

公开(公告)号：US11791219B2

公开(公告)日：2023-10-17

申请号：US17981499

申请日：2022-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

公开(公告)号：US11784238B2

公开(公告)日：2023-10-10

申请号：US17705416

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40

CPC classification number: H01L29/66462 ,  H01L29/201 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

公开(公告)号：US20230299166A1

公开(公告)日：2023-09-21

申请号：US18201769

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66045 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.