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    DYNAMIC NODE TRAVERSAL ORDER FOR RAY TRACING
    151.
    发明公开
    DYNAMIC NODE TRAVERSAL ORDER FOR RAY TRACING 审中-公开

    公开(公告)号：US20240112392A1

    公开(公告)日：2024-04-04

    申请号：US17956567

    申请日：2022-09-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： David William John Pankratz ,  Konstantin I. Shkurko

    IPC: G06T15/06 ,  G06T15/50

    CPC classification number: G06T15/06 ,  G06T15/50

    Abstract: Devices and methods for node traversal for ray tracing are provided, which comprise casting a first ray in a space comprising objects represented by geometric shapes, traversing, for the first ray, at least one first node of an accelerated hierarchy structure representing an approximate volume of a group of the geometric shapes and a second node representing a volume of one of the geometric shapes, casting a second ray in the space, selecting, for the second ray, a starting node of traversal based on locations of intersection of the first ray and the second ray and an identifier which identifies one or more nodes intersected by the first ray and traversing, for the second ray, the accelerated hierarchy structure beginning at the starting node of traversal.

    MULTI-LEVEL STARVATION WIDGET
    152.
    发明公开
    MULTI-LEVEL STARVATION WIDGET 审中-公开

    公开(公告)号：US20240111684A1

    公开(公告)日：2024-04-04

    申请号：US17957479

    申请日：2022-09-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sankaranarayanan Gurumurthy ,  Anil Harwani

    IPC: G06F12/0897

    CPC classification number: G06F12/0897 ,  G06F2212/601

    Abstract: The disclosed method includes detecting a stalled memory request, for a first level cache within a cache hierarchy of a processor, that includes an outstanding memory request associated with a second level cache within the cache hierarchy that is higher than the first level cache. The method further includes indicating, to the second level cache, that the first level cache is experiencing a starvation issue due to stalled memory requests to enable the second level cache to perform starvation-remediation actions. Various other methods, systems, and computer-readable media are also disclosed.

    Runtime Flushing to Persistency in Heterogenous Systems
    154.
    发明公开
    Runtime Flushing to Persistency in Heterogenous Systems 审中-公开

    公开(公告)号：US20240111682A1

    公开(公告)日：2024-04-04

    申请号：US17957262

    申请日：2022-09-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander Joseph Branover

    IPC: G06F12/0891

    CPC classification number: G06F12/0891

    Abstract: Runtime flushing to persistency in heterogenous systems is described. In accordance with the described techniques, a system may include a persistent memory in electronic communication with at least one cache and a controller configured to command the at least one cache to flush dirty data to the persistent memory in response to a dirtiness of the at least one cache reaching a cache dirtiness threshold.

    Selecting Between Basic and Global Persistent Flush Modes
    155.
    发明公开
    Selecting Between Basic and Global Persistent Flush Modes 审中-公开

    公开(公告)号：US20240111680A1

    公开(公告)日：2024-04-04

    申请号：US17957205

    申请日：2022-09-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander Joseph Branover

    IPC: G06F12/0868 ,  G06F12/084

    CPC classification number: G06F12/0868 ,  G06F12/084 ,  G06F2212/1032

    Abstract: Selecting between basic and global persistent flush modes is described. In accordance with the described techniques, a system includes a data fabric in electronic communication with at least one cache and a controller configured to select between operating in a global persistent flush mode and a basic persistent flush mode based on an available flushing latency of the system, control the at least one cache to flush dirty data to the data fabric in response to a flush event trigger while operating in the global persistent flush mode, and transmit a signal to switch control to an application to flush the dirty data from the at least one cache to the data fabric while operating in the basic persistent flush mode.

    BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION
    158.
    发明公开
    BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION 审中-公开

    公开(公告)号：US20240111489A1

    公开(公告)日：2024-04-04

    申请号：US17955634

    申请日：2022-09-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Onur Kayiran ,  Michael Estlick ,  Masab Ahmad ,  Gabriel H. Loh

    IPC: G06F7/498 ,  G06F7/506

    CPC classification number: G06F7/4981 ,  G06F7/506

    Abstract: A processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value. Y is a multiple of X. The plurality of adders further generate first carry bits. The plurality of carry bit generation circuits is coupled to the plurality of adders, respectively, and receive the first carry bits. The plurality of carry bit generation circuits generate second carry bits based on the first carry bits. The plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.

    OFF-CHIP MEMORY SHARED BY MULTIPLE PROCESSING NODES
    159.
    发明公开
    OFF-CHIP MEMORY SHARED BY MULTIPLE PROCESSING NODES 审中-公开

    公开(公告)号：US20240111452A1

    公开(公告)日：2024-04-04

    申请号：US17937292

    申请日：2022-09-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Michael John Austin ,  Dmitri Tikhostoup

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

    Abstract: An apparatus and method for efficiently managing performance among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes at least a first processing node and a second processing node. While processing tasks, the first processing node uses a first memory and the second processing node uses a second memory. A first communication channel transfers data between the first processing node and the second processing node. The first processing node accesses the second memory using a second communication channel different from the first communication channel and supports point-to-point communication. The second memory services access requests from the first and second processing nodes as the access requests are received while foregoing access conflict detection. The first processing node accesses the second memory after determining a particular amount of time has elapsed after reception of an indication from the second processing node specifying that a particular task has begun.

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