公开(公告)号：US20190044454A1

公开(公告)日：2019-02-07

申请号：US16052177

申请日：2018-08-01

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frederic GAUTIER

IPC: H02M7/219 ,  G05F3/20 ,  H02M7/5387

Abstract: A rectifying element includes a MOS transistor series-connected with a Schottky diode. A bias voltage is applied between the control terminal of the MOS transistor and the terminal of the Schottky diode opposite to the transistor. A pair of the rectifying elements are substituted for diodes of a rectifying bridge circuit. Alternatively, the control terminal bias is supplied from a cross-coupling against the Schottky diodes. In another implementation, theSchottky diodes are omitted and the bias voltage applied to control terminals of the MOS transistors is switched in response to cross-coupled divided source-drain voltages of the MOS transistors. The circuits form components of a power converter.

公开(公告)号：US20190019687A1

公开(公告)日：2019-01-17

申请号：US16033334

申请日：2018-07-12

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mathieu ROUVIERE ,  Mohamed BOUFNICHEL ,  Eric LACONDE

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/3105

Abstract: Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.

公开(公告)号：US20190013544A1

公开(公告)日：2019-01-10

申请号：US16030441

申请日：2018-07-09

Applicant: STMicroelectronics (Tours) SAS

Inventor： Delphine GUY-BOUYSSOU

IPC: H01M10/0525 ,  H01M10/0562 ,  H01M10/0585 ,  H01M4/1391 ,  H01M4/1395 ,  H01M4/525 ,  H01M4/38

Abstract: A thin-film battery of lithium-free type includes a stack of a positive electrode made of LiCoO2, an electrolyte layer made of LiPON, and a negative electrode made of copper. An adhesive layer based on polyvinylidene chloride (PVDC) is positioned on a face of the negative electrode opposite the electrolyte layer.

公开(公告)号：US20180350793A1

公开(公告)日：2018-12-06

申请号：US16055635

申请日：2018-08-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L27/02 ,  H01L29/87 ,  H01L29/747 ,  H01L29/74 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/0248 ,  H01L29/41716 ,  H01L29/42308 ,  H01L29/7404 ,  H01L29/7416 ,  H01L29/747 ,  H01L29/87

Abstract: A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

公开(公告)号：US10068999B2

公开(公告)日：2018-09-04

申请号：US15142070

申请日：2016-04-29

Applicant: STMICROELECTRONICS (TOURS) SAS ,  UNIVERSITE FRANCOIS RABELAIS

Inventor： Samuel Menard ,  Gael Gautier

IPC: H01L29/74 ,  H01L29/66 ,  H01L29/747 ,  H01L29/06 ,  H01L29/167

Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.

公开(公告)号：US10033437B1

公开(公告)日：2018-07-24

申请号：US15702207

申请日：2017-09-12

Applicant: STMicroelectronics (Tours) SAS

Inventor： Igor Bimbaud ,  Eric Colleoni

IPC: H04M1/00 ,  H04B5/00 ,  G06K19/07 ,  H02J7/00 ,  H04M1/02 ,  H04B1/3888

Abstract: A case includes a base for receiving a portable phone and a flap hinged to the base and including a housing configured to receive a microcircuit card. A first contactless communication antenna is provided in the flap for coupling to an antenna of the microcircuit card. A second contactless communication antenna is provided in the base for coupling to an antenna of the portable phone. The first and second first contactless communication antennae are electrically connected to each other.

公开(公告)号：US20180166659A1

公开(公告)日：2018-06-14

申请号：US15893107

申请日：2018-02-09

Applicant: STMicroelectronics (Tours) SAS

Inventor： Alexis Durand ,  Franck Dosseul

IPC: H01M2/02 ,  H01M2/22 ,  H01M2/04 ,  H01M10/04

CPC classification number: H01M2/0202 ,  H01M2/0478 ,  H01M2/22 ,  H01M10/0436 ,  H01M2220/30

Abstract: An electronic device includes a flexible conductive member having a first length, and a battery substrate having a second length shorter or equal than the first length. There is an active battery on the battery substrate. An adhesive layer couples the active battery and the battery substrate to the flexible conductive member such that the active battery and the flexible conductive member are electrically coupled, and such that the flexible substrate encapsulates the active battery and the upper portion of the battery substrate without an intervening layer. The flexible conductive member includes an insulating flexible base layer having a conductive via formed therein. Upper and lower metallized layers are formed on the insulating flexible base layer and are electrically coupled to one another by the conductive via.

公开(公告)号：US09979298B2

公开(公告)日：2018-05-22

申请号：US15157711

申请日：2016-05-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Tours) SAS

Inventor： Roberto Larosa ,  Giulio Zoppi ,  Laurent Gonthier

IPC: H02M3/335 ,  H02M1/08 ,  H02M1/42 ,  H02M1/36 ,  H02M7/12 ,  H02M7/06 ,  H02M1/00

CPC classification number: H02M3/33507 ,  H02M1/08 ,  H02M1/081 ,  H02M1/36 ,  H02M1/42 ,  H02M7/062 ,  H02M7/125 ,  H02M2001/0006

Abstract: A rectifier bridge circuit includes a first SCR/IGBT switch and a second SCR/IGBT switch coupled to a circuit input to receive an ac input voltage. The first and second SCR/IGBT switches are alternatively switchable to generate a rectified voltage at a circuit output. Control currents coupled to control terminals of the first and second SCR/IGBT switches are power supply sourced from an auxiliary dc source generated by rectifying the ac input voltage. The control currents are generated by current sources coupled between the auxiliary dc source and the control terminals of the first and second SCR/IGBT switches. The current sources are selectively activatable to produce gating currents for switching on and off the first and second SCR/IGBT switches. A controller unit is provided to control the current sources via level shifter circuits. The control implements progressive conduction time of the first and second SCR/IGBT switches so as to provide inrush current limitation.

公开(公告)号：US09912249B2

公开(公告)日：2018-03-06

申请号：US15140163

申请日：2016-04-27

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ghafour Benabdelaziz ,  Laurent Gonthier

IPC: H02M7/06 ,  H02M1/42 ,  H02M1/36 ,  H02M1/32 ,  H02M1/08

CPC classification number: H02M7/06 ,  H02M1/08 ,  H02M1/32 ,  H02M1/36 ,  H02M1/42 ,  H02M7/1623

Abstract: A rectifying circuit including: between a first terminal of application of an AC voltage and a first rectified voltage delivery terminal, at least one first diode; and between a second terminal of application of the AC voltage and a second rectified voltage delivery terminal, at least one first anode-gate thyristor, the anode of the first thyristor being connected to the second rectified voltage delivery terminal; and at least one first stage for controlling the first thyristor, including: a first transistor coupling the thyristor gate to a terminal of delivery of a potential which is negative with respect to the potential of the second rectified voltage delivery terminal; and a second transistor connecting a control terminal of the first transistor to a terminal for delivering a potential which is positive with respect to the potential of the second rectified voltage delivery terminal, the anode of the first thyristor being connected to the common potential of voltages defined by said positive and negative potentials.

公开(公告)号：US20180048019A1

公开(公告)日：2018-02-15

申请号：US15790529

申请日：2017-10-23

Applicant: STMicroelectronics (Tours) SAS

Inventor： Severin Larfaillou ,  Delphine Guy-Bouyssou

IPC: H01M10/052 ,  H01M4/1395 ,  H01M4/134 ,  H01M4/04 ,  H02J7/00 ,  H01M4/38 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/44 ,  H01M4/40

CPC classification number: H01M10/052 ,  H01M4/0445 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/38 ,  H01M4/382 ,  H01M4/405 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/44 ,  H02J7/007

Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.